Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-12-20
2003-03-25
Clark, Sheila V. (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S778000
Reexamination Certificate
active
06538315
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which is packaged for the mounting of a semiconductor component onto a circuit substrate, and to a method of manufacturing the same.
2. Description of the Related Art
There have been developed many types of packaging technologies including, as a typical one, quad flat pack (QFP). These packaging techniques are used to provide, at the time of mounting a semiconductor component onto a circuit substrate, facilitation of the protection and the mounting of semiconductor components. Because of the increase in connection terminal count in semiconductor components, the package size of semiconductor components is on the increase. Accordingly, it is becoming difficult for such conventional packaging technologies to deal effectively with demands for the reduction of mounting area.
With a view to meeting the demands, there has been devised a technique in which a bare semiconductor component is directly mounted onto a circuit substrate for the reduction and effective use of mounting area. For example, when a semiconductor component is connected to a circuit substrate, a layer of vapor-deposited adhesive metal or a layer of vapor-deposited diffusion protection metal is preformed on a terminal electrode of the semiconductor component and a projecting electrode of solder formed by plating is constructed overlying the layer. Subsequently, the semiconductor component is faced down and heated up to a high temperature. As a result of such application of heat, the solder is fused to a connection electrode of the circuit substrate. Such a mounting method is considered an effective technique because it can provide high post-connection mechanical strength and establish connection in a single process (“IC MOUNTING TECHNOLOGY”, edited by Japan Microelectronics Association, published on Jan. 15, 1980, Institute for Industrial Research).
In addition to the above-described method, there have been proposed other methods. For instance, U.S. Pat. No. 5,121,190 and Japanese Patent Application (unexamined) Pub. No. 6-61303 show mounting techniques and semiconductor devices in which a molding compound is used to secure the stability of solder joints. One such conventional semiconductor device will be described-below by reference to
FIGS. 7 and 8
.
FIG. 7
shows a layout of terminal electrodes of a commonly-used semiconductor component.
FIG. 8
shows in cross section major parts of a conventional semiconductor device with a semiconductor component mounted face down.
In the terminal electrode layout of
FIG. 7
, terminal electrodes
16
are laid out around the periphery of a semiconductor component
15
. In order to deal with an increase in the number of terminal electrodes
16
, it is required to either reduce the gap between terminal electrodes
16
or increase the size of the semiconductor component
15
for coping with such an electrode number increase.
The semiconductor device of
FIG. 8
, in which the semiconductor component
15
is mounted face down, comprises, in addition to the semiconductor component
15
, a terminal electrode
16
of the semiconductor component
15
, a circuit substrate
17
, a connection electrode
18
formed on a surface of the circuit substrate
17
, a solder joint
19
which joints together the connection electrode
18
and the terminal electrode
16
, a molding (sealing) resin
20
which seals the semiconductor component
15
, and other structural elements.
A method of manufacturing a conventional semiconductor device having the above-described structure will be described below. In the first place, a projecting electrode of solder is preformed on the terminal electrode
16
of the semiconductor component
15
. Thereafter, the semiconductor component
15
is mounted, in face down fashion, onto the circuit substrate
17
. This is followed by alignment of the solder projecting electrode with a given position of the connection electrode
18
. Next, the solder is melted by application of high-temperature heat (from 200 to 300 degrees centigrade), and the solder projecting electrode and the connection electrode
18
are joined together. In this way, the semiconductor component
15
is fixed to the circuit substrate
17
by the solder joint
19
. Thereafter, a gap, created between the semiconductor component
15
and the circuit substrate
17
, is filled with the molding resin
20
in the form of liquid. By heat hardening at about 120 degrees centigrade, the molding resin
20
is solidified. In this way, the mounting of the semiconductor component
15
onto the circuit substrate
17
is completed to provide a semiconductor device as shown in FIG.
8
.
However, the above-described conventional semiconductor devices and associated manufacture methods have the following drawbacks.
Firstly, in order to protect the surface of the semiconductor component
15
, it is required to fill a gap between the semiconductor component
15
and the circuit substrate
17
with the molding resin
20
, and the mounting size increases accordingly. Therefore, when used as a packaged semiconductor device, its size becomes greater than that of the semiconductor component
15
.
Secondly, if the number of terminal electrodes
16
of the semiconductor component
15
increases as the circuit scale increases, then the gap between adjacent terminal electrodes
16
is made narrower, resulting in reducing the size and the pitch of the solder joint
19
and consequently the reliability of the solder joint
19
between the semiconductor component
15
and the circuit substrate
17
will drop.
Thirdly, in order to facilitate the mounting of the terminal electrodes
16
laid out around the periphery of the semiconductor component
15
in face-down manner, it is required to use a multi-level wiring technique making use of a thin film technology for two-dimensionally placing the terminal electrodes
16
on the semiconductor component
15
, to increase the size and the pitch of the terminal electrodes
16
. However, such arrangement produces some problems, that is, semiconductor device yield is decreased and manufacturing costs are increased.
In view of the above, there is the limit of down-sizing semiconductor devices, improving their reliability to a further extent, and reducing their production costs and therefore the foregoing prior art techniques are not very practical. Particularly, in order to deal with the increase in the number of terminals in a semiconductor component, the above-described problems become increasingly serious.
SUMMARY OF THE INVENTION
The present invention was made with a view to providing solutions to the foregoing problems with the prior art techniques. Accordingly, an object of the present invention is to provide a down-sized, thinned, highly-reliable semiconductor device capable of dealing with higher terminal count, and a method of manufacturing the same. The
Therfor—one aspect invention of the present invention is a semiconductor device comprising:
(a) a semiconductor component;
(b) a circuit substrate;
(c) a base material which is placed between said semiconductor component and said circuit substrate; and
(d) a conductive paste, which is filled into a hole formed in said base material, for electrically connecting between a terminal electrode of said semiconductor component and an internal connection electrode of said circuit substrate.
Therefor—another aspect of the present invention is a semiconductor device comprising:
(a) a semiconductor component;
(b) a circuit substrate; and
(c) a conductive paste, which is filled into a hole formed in a surface of said circuit substrate at the side of said semiconductor component, for electrically connecting between a terminal electrode of said semiconductor component and an external connection electrode of said circuit substrate.
Therefor—still another aspect of the present invention is a method of manufacturing a semiconductor device in which a semiconductor component is mounted onto a circuit substrate, said semiconductor device manufacture
Bessho Yoshihiro
Itagaki Minehiro
Clark Sheila V.
Matsushita Electric - Industrial Co., Ltd.
RatnerPrestia
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