Superposition of host bridge status onto an existing...

Details Superposition of host bridge status onto an existing... Superposition of host bridge status onto an existing...

1997-01-15

2003-03-04

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S110000, C710S309000

Reexamination Certificate

active

06529980

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of computer systems. More specifically, the present invention relates to an arbitration scheme between multiple bus agents
BACKGROUND OF THE INVENTION
In addition to including a host bus and a memory bus, many computer systems include an Industry Standard Architecture (“ISA”) bus, a Peripheral Component Interconnect (“PCI”) bus, or both an ISA and a PCI bus. Peripheral or memory devices that are compatible with the ISA bus may be coupled to the computer system through the ISA bus while peripheral or memory devices that are compatible with the PCI bus may be coupled to the computer s stem through the PCI bus. Typically, the devices coupled to a bus are referred to as bus agents. A bus agent may be a bus master (i.e., a bus agent that initiates a bus transaction) or a target agent (i.e., a bus agent that is the target of the bus transaction initiated by the bus master agent). When a PCI bus is added to a system that already includes an ISA bus, the PCI bus may be referred to as an intermediate or local bus. As more buses are added to a computer system, a more complex arbitration scheme may need to be implemented in order to maintain system coherency.
FIG. 1
illustrates a computer system
100
that includes an ISA Bus
108
. The central processing unit
101
(“CPU”) is coupled to the Host-to-ISA (“Host-ISA”) Bridge
102
, via the Host Bus
106
, and the Main Memory
103
is coupled to the Host-ISA Bridge
102
via the Memory Bus
105
. The Host-ISA Bridge
102
includes the Arbitration Logic
104
. When an ISA direct memory access (“DMA”) Agent, such as Agent
107
, requests DMA service in order to access the Main Memory
103
, the ISA DMA Agent
107
asserts the request line
113
(“DREQ”), and subsequently, the Host-ISA Bridge
102
asserts the hold line
111
(“HOLD”). When the CPU
101
returns an asserted hold acknowledge line
110
(“HOLDACK”), the Host-ISA Bridge
102
is informed that the CPU
101
will no longer initiate cycles from the CPU
101
to the Main Memory
103
or ISA Bus
108
. The Host-ISA Bridge
102
then proceeds to assert the acknowledge line
112
(“DACK#”) to inform the ISA DMA Agent
107
that the DMA transaction is now beginning.
The computer system
100
requires a relatively simple arbitration scheme because there are only, two possible types of masters—the CPU and the ISA agents. Typically, in the computer system
100
, any potential flushes (i.e., buffered writes from the CPU are transferred to their target ISA agents before granting the ISA agent bus mastership) may be performed by the Host-ISA Bridge
102
. This buffering policy typically does not run into the condition where an ISA DMA Agent
107
cannot access the Main Memory
103
.
On the other hand, when an intermediate bus, such as the PCI Bus
209
, is interposed between the ISA Bus
214
and the CPU
201
, the arbitration scheme may also be required to ensure system coherency. This type of arbitration scheme may be more complex because under certain conditions, an ISA agent may not be able to access the main memory without causing system failure conditions, such as system deadlock or system livelock.
FIG. 2
illustrates a computer system
200
that includes both a PCI bus
209
and an ISA bus
214
.
The Host-to-PCI (“Host-PCI”) Bridge
202
is coupled to the CPU
201
via the Host Bus
204
and to the Main Memory
203
via the Memory Bus
205
. The Main Memory
203
may be dynamic random access memory (“DRAM”) for providing dynamic storage for run-time computer events. The PCI arbiter
207
and the CPU-to-PCI Buffer
208
resides within the Host-PCI Bridge
202
. The PCI arbiter
207
arbitrates the use of the PCI bus
209
and the CPU-to-PCI Buffer
208
is used to buffer data writes (i.e., posted writes) from the CPU
201
which are destined for the PCI bus
209
or ISA Bus
214
. Typically, the PCI agent
206
receives PCI bus mastership after the PCI agent
206
asserts the request line
223
(“REQ#), and subsequently, the PCI Arbiter
207
asserts the grant line
222
(“GNT#) which is received by the PCI agent
207
.
The Host-PCI Bridge
202
is coupled to the PCI agents via the PCI Bus
209
. For example, the PCI Master Agent
206
and the PCI Target Agent
211
may reside on the PCI Bus
209
. Other PCI agents may also reside on the PCI Bus
209
. The PCI Bus,
209
is referred to herein as a “pre-emptible” bus because it may suspend the operation of one PCI agent when another operation from another PCI gent demands use of the PCI bus
209
to access the various system resources.
The PCI-to-ISA (“PCI-ISA”) Bridge
210
is coupled to the PCI Bus
209
to provide an expansion bridge for an ISA Bus
214
. The ISA Bus
214
is referred to herein as a “non-pre-emptible” bus because when an ISA agent, such as the ISA DMA Agent
213
, is granted access to the ISA Bus
214
, the computer system locks out all other agents and all other buses, as well as the CPU
201
and the Main Memory
203
, until the transaction for which the ISA agent was granted access has been entirely completed. This lock out feature of the ISA Bus
214
may be referred to as guaranteed access timing because the ISA agent is guaranteed system ownership for undefined periods of time w th guaranteed DRAM access.
The ISA Arbiter
212
may reside with the PCI-ISA Bridge
210
and may be used to arbitrate for he use of the ISA Bus
214
. Various agents, such as the ISA DMA Agent
213
and the ISA Target Agent
215
, may reside on the ISA Bus
214
. Other ISA agents may also reside on the ISA Bus
214
. Typically, the ISA DMA Agent
213
may access the Main Memory
203
after the ISA DMA Agent
213
asserts the request line
224
(“DREQ”) and subsequently, the PCI-ISA Bridge
210
asserts the acknowledge or grant line
225
(DACK#) which is received by the ISA DMA Agent
213
.
Unfortunately, when a pre-emptible bus, such as the PCI Bus
209
and a non-pre-emptible bus, such as an ISA Bus
214
, are both incorporated into a compute system, failure conditions (e.g., system livelock and deadlock) may arise in which the ISA DMA Agent
213
may not be able to access the Mail Memory
203
. For example, the ISA DMA Agent
213
may not access the Main Memory
203
for reads when the Host-PCI Bridge
202
is storing posted writes in the CPU-to-PCI Buffer
208
. However, once the CPU-to-PCI Buffer
208
has completed all writes to the destined target agent(s), the ISA DMA Agent
213
may then access the Main Memory
203
. As such, these types of failure conditions may be eliminated by providing a unique arbitration scheme between the PCI-ISA Bridge
210
and the Host-PCI Bridge
202
.
Rather than incorporating the arbitration scheme that uses the PCI bus REQ# and GNT# signals as defined in the specification published by the PCI Special Interest Group in Portland, Oreg. (such as revisions 1.0 (1992) and 2.0 (1993) and 2.1 (1993)) the Host-PCI Bridge
202
and the PCI-ISA Bridge
210
may use the signals PHOLD# and PHLDA# which may be defined as PCI bus sideband signals. Typically, a sideband signal is defined as a signal that is not compliant with the PCI bus specification and is used to interconnect two or more PCI agents. In addition to providing the same functionality (i.e., request and grant) as the REQ# and GNT# signals, the PHOLD# signal and the PHLDA# signal provides the additional functionality of ensuring that the CPU-to-PCI Buffer
208
is flushed prior to granting PCI bus mastership to the PCI-ISA Bridge
210
in order to maintain system coherency. The PHOLD# and the PHLDA# signals are described below.
FIG. 3
illustrates a DMA operation requested by the ISA DMA Agent
213
. The ISA DMA Agent
213
asserts the DREQ signal
304
when it is requesting data transfers involving the Main Memory
203
(see time index A). The PHOLD# signal
301
is asserted in response to the assertion of the DREQ signal
304
, as shown by the arrow
310
(see time index B).
In response to the assertion of the PHOLD&nu

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