Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-12-21
2003-04-29
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S110000, C438S113000, C438S458000
Reexamination Certificate
active
06555416
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a chip size package semiconductor device and a method of forming the same.
The chip size package is a package minimized in size and weight. There have been known various types of the chip size packages. Some kinds of the conventional chip size packages will be described with reference to the accompanying drawings.
FIG. 1
is a cross sectional elevation view illustrative of a first conventional chip size package. A silicon chip
2
is bonded onto a printed wiring board
14
by a flip chip bonding method. The silicon chip
2
has a flip chip bonding surface which has electrode pads on which gold bumps
13
are formed. The printed wiring board
14
also has a flip chip bonding surface which has bonding pads
15
. The silicon chip
2
is bonded onto the printed wiring board
14
through the gold bumps
13
, whereby a gap or a space is formed between the silicon chip
2
and the printed wiring board
14
. The gap or space between the silicon chip
2
and the printed wiring board
14
is sealed with a sealing resin
12
. The printed wiring board
14
has an opposite surface to the flip chip bonding surface, wherein the opposite surface has an array of solder balls
20
which has a larger pitch than the electrode pad pitch of the silicon chip
2
, so as to enable the printed wiring board
14
to make an electrical connection through the larger-pitched solder balls
20
to a mother board not illustrated, wherein the printed wiring board
14
serves as an interposer. This interposer allows the electrode pitch of the silicon chip to be much more narrowed than the necessary pitch of the solder balls
20
for the required external connection to the mother board.
FIG. 2
is a cross sectional elevation view illustrative of a second conventional chip size package. A silicon chip
2
is bonded onto a carrier tape
18
. The silicon chip
2
has a bonding surface which has electrode pads on which gold bumps
13
are formed. The carrier tape
18
also has a bonding surface bonded with the silicon chip
2
. The silicon chip
2
is bonded onto the carrier tape
18
through the gold bumps
13
and an adhesive
17
. The carrier tape
18
also has an opposite surface to the bonding surface, wherein the opposite surface has an array of solder balls
20
which has a larger pitch than the electrode pad pitch of the silicon chip
2
, so as to enable the carrier tape
18
to make an electrical connection through the larger-pitched solder balls
20
to a mother board not illustrated, wherein the carrier tape
18
serves as an interposer. The interposer allows the electrode pitch of the silicon chip to be much more narrowed than the necessary pitch of the solder balls
20
for the required external connection to the mother board the silicon chip is covered by a cover
16
.
FIG. 3
is a cross sectional elevation view illustrative of a third conventional chip size package. A silicon chip
2
is bonded onto a printed wiring board
14
by a face-up bonding method. The silicon chip
2
has a face-up bonding surface which has electrode pads. The printed wiring board
14
also has a bonding surface which has bonding pads. The silicon chip
2
is placed on the printed wiring board
14
so that the electrode pads on the face-up bonding face are bonded through gold wirings
19
to the pads of the printed wiring board
14
. The face-up bonding face of the silicon chip
2
and the pads of the printed wiring board
14
are sealed with a sealing resin
26
so that the gold wirings
19
are buried within the sealing resin
26
. The printed wiring board
14
has an opposite surface to the bonding surface, wherein the opposite surface has an array of solder balls
20
which has a larger pitch than the electrode pad pitch of the silicon chip
2
, so as to enable the printed wiring board
14
to make an electrical connection through the larger-pitched solder balls
20
to the mother board, wherein the printed wiring board
14
serves as an interposer. This interposer allows the electrode pitch of the silicon chip to be much more narrowed than the necessary pitch of the solder balls
20
for the required external connection to the mother board.
Further, in Japanese laid-open patent publication No. 7-231020, a fourth conventional chip size package is disclosed, wherein projecting bonding pads are formed on a bonding face of the silicon chip so that the bonding pads of the silicon chip are bonded through a pre-preg layer to bumps on a bonding face of a printed wiring board which further has an opposite face to the bonding face, where the opposite face has area pads.
When the second conventional chip size package is bounded on the mother board, a thermal expansion coefficient of the silicon chip
2
suppresses a thermal expansion coefficient of the carrier tape
18
, resulting in a large difference in thermal expansion coefficient of the carrier tape
18
from the mother board. The large difference in thermal expansion coefficient of the carrier tape
18
from the mother board results in application of a large stress to the solder balls
20
in a test, whereby a crack is formed at connecting portions of the solder balls
20
. As a result, an electrical disconnection might appear. In order to solve this problem, a resin with a low elasticity is inserted into a gap between the carrier tape
18
and the silicon chip
2
. This conventional technique is disclosed in Japanese laid-open patent publication No. 8-504063.
An area array of external contacts on a silicon chip was proposed so called as “C4”. This “C4” process has been practiced by IBM Corporation.
The foregoing conventional chip size packages have the following problems.
In order to form the conventional chip size packages, the silicon chip is bonded on the interposer such as the printed wiring board or the carrier tape and further the interposer with the silicon chip is mounted on the mother board. Namely, the silicon chip is bonded through the interposer onto the mother board, for which reason it is difficult for the conventional chip size packages to reduce the size, thickness, weight and the manufacturing cost. Namely, the interposer such as the printed wiring board or the carrier tape increases the size, thickness, weight and the manufacturing cost.
In accordance with the above “C4” process, external connective contacts are formed on an insulating film of the silicon chip, for which reason when the package is mounted on the mother board, a gap is formed between the package and the mother board. This gap is required to be sealed with a sealing resin. This increases the manufacturing cost and also makes it difficult to repair defective part of the package. Namely, the insulation film is an insulation film normally and often used in the manufacturing processes of the silicon chip. This insulating film has a high elastic constant. This insulating film is thin and a thickness is not larger than 10 micrometers. For those reasons, this insulating film is incapable of realization of the above thermal stress due to the large difference in thermal expansion efficient between the silicon chip and the mother board. It is therefore required to seal the gap between the silicon chip and the mother board with the sealing resin. Namely, the silicon chip and the mother board are bonded by the sealing resin, for which reason it is difficult to repair a defective part of the package.
As in the “C4” type package, the resin layer as the insulating layer is formed on the silicon wafer and further the external connective contacts are formed on the resin layer before the silicon wafer is cut to form silicon chips, whereby parts of the silicon chip circuit are shown on the cutting section. The resin is built up over the silicon wafer to form external connective electrode contacts before the wafer is cut by dicer to form chips, whereby the cutting sections are exposed to atmosphere having a high humidity.
In the above circumstances, it had been required to develop a novel chip size package free from the above problems.
SUMMARY OF THE IN
Nakamura Hirofumi
Tago Masamoto
Geyer Scott B.
NEC Corporation
Sughrue & Mion, PLLC
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