Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-03
2003-03-04
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000, C257S319000, C257S320000, C257S321000
Reexamination Certificate
active
06528843
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a split-gate flash memory cell and its flash memory array and, more particularly, to a self-aligned split-gate flash memory cell having a single-side tip-shaped floating-gate structure and its contactless flash memory arrays.
DESCRIPTION OF THE RELATED ART
A flash memory cell structure can be basically divided into two categories: a stack-gate structure and a split-gate structure, in which the gate length of a stack-gate structure can be defined by using a minimum-feature-size (F) of technology used and, therefore, the stack-gate structure is often used in existing high-density flash memory system for mass storage applications. The stack-gate flash memory cells can be configured into an array of a matrix form according to the basic logic function, such as NOR-type, NAND-type or AND-type. In general, a stack-gate flash memory cell in a NOR-type or AND-type array is programmed by the channel hot-electron injection (CHEI), however the programming efficiency is low and the programming power is large. Moreover, the gate length of a stack-gate flash memory cell is difficult to be scaled down due to the punch-through effect if the channel hot-electron injection is used as a programming method. For a NAND-type array, the stack-gate flash memory cells are interconnected in series with common-source/drain diffusion regions, the density is high but the read speed is relatively slow as compared to that of a NOR-type array. Moreover, the programming speed of a NAND-type array is relatively slow due to the Fowler-Nordheim tunneling across the thin tunneling-oxide layer between the source/drain diffusion region and the floating gate being used as a programming method.
The split-gate structure having a select-gate region and a stack-gate region offers in general a larger cell size as compared to that of a stack-gate structure and is usually configured to be a NOR-type array. Two typical split-gate flash memory cell structures are shown in FIG.
1
A and FIG.
1
B.
FIG. 1A
shows a split-gate flash memory device having the floating-gate layer
11
formed by a local-oxidation of silicon (LOCOS) technique, in which the floating-gate length is defined in general to be larger than a minimum-feature-size of technology used due to the bird's beak formation; the control-gate
15
is formed over a LOCOS-oxide layer
12
and a thicker select-gate oxide layer
14
; a poly-oxide layer
13
is formed over a sidewall of the floating-gate layer
11
; a source diffusion region
16
and a drain diffusion region
17
are formed in a semiconductor substrate
100
in a self-aligned manner; and a thin gate-oxide layer
10
is formed under the floating-gate
11
. The split-gate structure shown in
FIG. 1A
is programmed by mid-channel hot-electron injection, the programming efficiency is high and the programming power is low as compared to the channel hot-electron injection used by the stack-gate structure. Moreover, the over-erase problem of the split-gate structure can be prevented due to a high threshold-voltage for the select-gate region, so the control logic circuits for erasing and verification can be simplified. However, there are several drawbacks for FIG.
1
A: the cell size is larger due to the non self-aligned control-gate structure; the gate length can't be easily scaled down due to the misalignment of the control-gate with respect to the floating-gate; the coupling ratio is low and higher applied control-gate voltage is required for back erase; and the field-emission tip of the floating-gate layer is difficult to be controlled due to the weak masking ability of the bird-beak oxide.
FIG. 1B
shows another split-gate structure, in which the floating-gate layer
21
is defined by a minimum-feature-size (F) of technology used; a thin tunneling-oxide layer
20
is formed under the floating-gate layer
21
; a select-gate dielectric layer
22
is formed over the select-gate region and the exposed floating-gate layer
21
; a control-gate layer
23
is formed over the select-gate dielectric layer
22
; and a source diffusion region
24
and a double-diffused drain region
25
,
26
are formed in a semiconductor substrate
100
. From
FIG. 1B
, it is clearly visualized that similar drawbacks as listed for
FIG. 1A
are appeared except that the erasing site is located at the thin tunneling-oxide layer
20
between the floating-gate layer
21
and the double-diffused drain region
25
,
26
.
It is therefore an objective of the present invention to provide a self-aligned split-gate flash memory cell having a cell size being smaller than 4F
2
.
It is another objective of the present invention to provide a higher coupling ratio for a self-aligned split-gate flash memory cell.
It is a further objective of the present invention to provide a reproducible tip-cathode structure for the self-aligned split-gate flash memory cell with a higher field-emission efficiency.
It is yet another objective of the present invention to provide two contactless architectures for self-aligned split-gate flash memory arrays.
Other objectives and advantages of the present invention will be more apparent from the following description.
SUMMARY OF THE INVENTION
A self-aligned split-gate flash memory cell of the present invention is formed on a semiconductor substrate of a first conductivity type having an active region isolated by the two parallel shallow-trench-isolation (STI) regions, wherein each of two parallel STI regions is filled with a first raised field-oxide layer. A cell region can be divided into three regions: a common-source region, a gate region, and a common-drain region, wherein the gate region is located between the common-source region and the common-drain region. The common-source region comprises a first sidewall dielectric spacer being formed over a sidewall of the gate region and on a portion of a first flat bed being formed by a common-source diffusion region of a second conductivity type in the active region and two etched first raised field-oxide layers in the two parallel STI regions. The common-drain region comprises a second sidewall dielectric spacer being formed over another sidewall of the gate region and on a portion of a second flat bed being alternately formed by a common-drain diffusion region of the second conductivity type in the active region and two etched second raised field-oxide layers in the two parallel STI regions. The gate region comprises a planarized control/select-gate conductive layer having a portion formed at least on a second gate-dielectric layer in a select-gate region and another portion formed at least on a single-side tip-shaped floating-gate structure being formed on a first gate-dielectric layer in a stack-gate region; a bird-beak shaped oxide layer being formed over the single-side tip-shaped floating-gate structure to act as a first intergate-dielectric layer in the stack-gate region or the bird-beak shaped oxide layer being removed and replaced by a dielectric layer as the first intergate-dielectric layer; and a second intergate-dielectric layer being formed over an inner sidewall between the single-side tip-shaped floating-gate structure and the planarized control/select-gate conductive layer.
The self-aligned split-gate flash memory cell of the present invention as described is used to implement two contactless array architectures: a NOR-type flash memory array and a parallel common-source/drain conducive bit-lines flash memory array. The contactless NOR-type flash memory array comprises a plurality of common-source conductive bus lines being formed alternately in a first direction; a plurality of common-drain conductive islands being at least formed over the plurality of active regions along each of the common-drain regions between the plurality of common-source conductive bus lines; a plurality of self-aligned split-gate flash memory cells being formed between each of the plurality of common-source conductive bus lines and its nearby common-drain conductive islands with the elongated planarized control/select-gate
Silicon Based Technology Corp.
Thomas Tom
Tran Thien F
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