Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2001-06-12
2003-03-18
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S189080, C365S203000, C365S214000
Reexamination Certificate
active
06535444
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to electronic circuits, and, more particularly, to dynamic random access memories (DRAMs). In particular, the invention relates to the control of the read/rewrite accesses and the pre-charging of reference cells associated with memory cells of a DRAM.
BACKGROUND OF THE INVENTION
The invention applies advantageously, but not limitingly, to so-called “embedded” dynamic memories. That is, the invention relates to memories made jointly with other components by the same technological process and which are intended to be integrated together within an application specific integrated circuit (ASIC), for example.
In static random access memories (SRAMs), information stored therein remains stored indefinitely, i.e., at least as long as the memory remains energized. On the other hand, dynamic memories require a periodic refreshing of the information stored therein due, in particular, to the stray leakage currents which discharge the storage capacitance of each memory cell.
Among dynamic random access memory cells, particular mention is made here of those including one, two or three transistors. Conventionally, dynamic random access memories are arranged in rows and columns of memory cells. Each column includes a metallization commonly referred to as the “bit line” and an immediately adjacent bit line referred to as the reference bit line or “bit line complement.” Moreover, means for column-wise pre-charging provide pre-charging of the bit line and the reference bit line of the column before a read access of the memory. The bit line pre-charging and the pre-charging of the reference bit line are generally performed at a voltage equal to Vdd/2, where the supply voltage Vdd represents the storage voltage of a high state (typically a logic “1”) and 0 volts (ground) represents the storage voltage of a low state (typically a logic “0”).
Most DRAM memories use a row of so-called “reference” cells, also connected to the bit lines and the reference bit lines, to equalize the charges of the bit lines and the reference bit lines. The reference cells also maximize the average amplitude of the signal between 0 and 1. Other pre-charging means are also provided for pre-charging the row of reference cells. The pre-charging of the reference cells is also performed generally at Vdd/2.
During a read access of a memory cell connected to a bit line, this memory cell and the reference cell connected to the reference bit line are selected (i.e., activated). Then the sign of the voltage difference between the bit line and the reference bit line is detected to determine the logic content (0 or 1) of the memory cell. This detection is conventionally performed with the aid of a read/rewrite amplifier connected between the bit line and the reference bit line. This amplifier generally includes two looped-back inverters (forming a bistable flip-flop), each formed by two complementary transistors and controlled by two successive signals read and rewrite (commonly known as “sense” and “restore,” respectively).
Upon activation of the restore signal, the datum read from the memory is rewritten, thereby refreshing the contents of this cell. A conventional memory structure of this kind has certain drawbacks. A first drawback lies in the value of the voltage for pre-charging the reference cells. Specifically, by reason of the stray leakage currents which discharge the storage capacitance of each cell storing a logic “1” (i.e., in N-channel metal-oxide semiconductor (NMOS) technology), the voltage of the bit line is less than Vdd when the memory cell is selected. Also, the voltage difference between the bit line and the reference bit line may be reduced thereby when reading the memory cell.
This is especially troublesome if this voltage difference becomes less than the offset voltage of the read/rewrite amplifier since this may lead to erroneous refreshing of the memory cell (i.e., a 1 is rewritten whereas a “0” is read and vice-versa). This problem may arise in a memory which remains inactive (i.e., without read access) for a relatively long time. It may also occur in an embedded DRAM memory for which the process used is geared more towards the speed of propagation of the signals, consequently leading to an increase in the leakage currents.
A second drawback of the structure of the above prior art device lies in the means used for providing the return to the pre-charge value of the reference cells. Specifically, this return is ensured by the use of a DC voltage generator which is common to all the reference cells. However, the design of such a generator is especially difficult due particularly to the considerable charging capacitance (typically 1024 reference cells each having a capacitance of 30 fF), of the large voltage excursion required, and of the high frequencies (e.g., 50-100 MHz for current generations of memory).
The design of such a generator is all the more difficult at low voltages, and the static consumption may be too high to attain the necessary performance. Furthermore, it is especially difficult to distribute the voltage generated across the entire memory by the stray capacitances and miscellaneous resistances. Additionally, the pre-charging operation is greatly dependent upon the data read or written. The invention addresses the above problems.
SUMMARY OF THE INVENTION
An object of the invention is to pre-charge the reference cells of a memory to a pre-charge value which makes reading of the data less sensitive to current leakage.
Another object of the invention is to avoid the use of a DC generator for establishing the pre-charge potential for the reference cells, i.e., for pre-charging these cells.
Yet another object of the invention is to provide a pre-charging mechanism which is effective at low voltages and relatively faster than prior art devices, thus providing an increase in the operating frequency of the memory.
According to the invention, a method is for controlling a read access of a memory cell of a memory plane of a dynamic random access memory. In such a memory, the memory cell is connected to a bit line of the memory plane and associated with a main reference cell connected to a reference bit line. This process includes a phase of reading and refreshing the contents of the memory cell and a phase of pre-charging the bit line, the reference bit line, and the main reference cell with a view to a subsequent read access.
In the course of the phase of reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line are activated. After having deactivated the two reference cells, the main reference cell and secondary reference cell are pre-charged to a final pre-charge voltage chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of the high-state storage voltage and the low-state storage voltage. This is done by linking the main reference cell and secondary reference cell to a capacitive line separate from the bit line and from the reference bit line and having a predetermined potential and a predetermined capacitive value.
The invention therefore uses a charge sharing mechanism for pre-charging the reference cells. This charge sharing mechanism is especially effective at low voltage. It is instigated locally, thus allowing an increase in performance (faster pre-charging). This gives rise to an increase in the operating frequency of the memory. It is therefore unnecessary to provide a DC generator to establish the pre-charge potential for the reference cells. As such, an economy of consumption as well as an area savings is achieved.
Moreover, charge sharing using a capacitive line having a predetermined potential and a predetermined capacitive value makes it possible to pre-charge the reference cells to a pre-charge voltage different from half the sum of the high-state storage voltage and the low-state storage voltage (typically different from Vdd/2). Thus, by way of example, the final pre-charge voltage of the reference cells may be
Goducheau Olivier
Jacquet François
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Lebentritt Michael S.
Nguyen Van-Thu
STMicroelectronics S.A.
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