High dielectric constant metal oxide gate dielectrics

Details High dielectric constant metal oxide gate dielectrics High dielectric constant metal oxide gate dielectrics

1998-12-15

2003-03-04

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S410000, C438S287000, C438S591000

Reexamination Certificate

active

06528856

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly the invention relates to the formation of metal oxide gate dielectric layers for metal-oxide-semiconductor field effect transistors (MOSFETs).
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the line widths of the various parts that make up an integrated circuit. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors.
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, these devices are referred to simply as FETs, and are so referred to herein.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate dielectric thickness are also typically reduced in order to produce a FET with the desired electrical characteristics. Similarly, when in use, these reduced scale FETs are operated with scaled down voltages.
Over the years, a substantial amount of research and development in the field of semiconductor manufacturing has been dedicated to providing reduced thickness dielectric layers, as mentioned above. However, to be suitable for use as a MOSFET gate dielectric layer, these reduced thickness dielectric layers are typically required to have certain characteristics. For example, the dielectric layer should have a low density of interface states, a low density of defects, and a dielectric breakdown voltage high enough for use with the desired voltages that the MOSFET will encounter during operation.
What is needed is a thin dielectric layer suitable for use as the gate dielectric layer in a MOSFET, and what is further needed are methods of making such a dielectric layer.
SUMMARY OF THE INVENTION
Briefly, a method of forming a dielectric layer suitable for use as the gate dielectric layer of a MOSFET includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form an at least partially epitaxial silicon layer superjacent the substrate, and a metal oxide layer superjacent the epitaxial silicon layer.
In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.


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