Solid state device

Details Solid state device Solid state device

2000-09-27

2003-07-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C257S140000, C257S146000

Reexamination Certificate

active

06599781

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to solid state integrated circuit devices and more particulary to improved, miniaturized semiconductor integrated circuit devices.
2. Description of Related Art
Shockley, Bardeen, and Brattain invented the transistor around 1950 and started the modern electronics age. Kilby and Noyce next combined active and passive components on a single chip and invented the integrated circuit. Fairchild's Isoplanar technology (
FIG. 1
) made possible medium-scale and larger-scale integrated circuits in 1972 according to Peltzer's U.S. Pat. No. 3,648,125. Simultaneously, other similar dielectric isolation processes such as Kooi's LOCOS (i.e., local oxide isolation technology) of Philip and Magdos's oxide-recessed technology of IBM were also widely used. In a 1976 Interference No. 98,426, Li's application No. 154,300 on round-bottomed isolating oxide groove was considered as the “Seniormost Inventor” among Fairchild's Peltzer, Philip's Kooi, and IBM's Magdo and Magdo.
According to Peltzer's patent, the Fairchild's Isoplanar device 40 as typified by FIG. 4 in his patent has a n-type epitaxial silicon layer 42 formed on a p-type substrate 41. Oxide isolating regions, e.g., 44
a,
44
b,
44
c,
and 44
d
were used to isolate the different components. Each of these oxide isolating regions has a central flat bottom occupying much chip real estate producing unnecessarily larger devices.
Li's round-bottomed isolating oxide groove 21 of FIG. 21 in 154,300 application improves device leakage current and breakdown voltage. The groove bottom G of zero width eliminates the wasted chip real estate of all other previously existing devices of, e.g., Isoplanar, LOCOS, and oxide-recessed types. This feature produces smaller devices. The oxide isolating regions in this present invention are further narrowed down to even one or two atomic layers occupying the minimum chip real estate. Li's devices also have rounded PN junction peripheral surfaces minimizing contamination by micron-size or even atomic particles thereby increasing yields. See FIG. 2. The smaller the device size, the more critical this yield factor.
In the 154,300 patent application, the device of FIG. 2 is made by thermally growing an oxide groove, band, or material region 21 transversely into a p-type silicon substrate 22. This is followed by oxide-guided, maskless diffusion of n-type dopants from the top surface 23 to give the top n-type silicon layer 24 and the new PN junction region 25. The rounded bottom G has a zero bottom width.
All these devices can still be improved in performance and device size. The present invention provides still better and further miniaturized solid-state integrated circuits in general and semiconductor integrated circuits in particular.
Specifically, this invention will address the following issues:
1) improving the critical gate layer thickness and structure;
2) reducing the insulating field oxide region size by orders of magnitude from microns to Angstroms;
3) making the entire device more resistant to temperature, stress, impact, vibration, and high-gravity (G) forces due to rapid acceleration and deceleration;
4) simplifying a device material inventories and manufacturing process;
5) providing a new type of high-performance flexible circuits; and
6) designing three-dimensional (3-D) atomic or molecular diode or transistor arrays or circuits especially useful for supercomputers and electro-optical telecommunications.
The devices of the invention may use different solid-state or semiconductor materials including Si, Ge, Si—Ge, InP, GaAs, SiC, InAs, superconductor, and diamond. In this invention, Si semiconductor materials are exclusively used by way of illustration. Metal-oxide-semiconductor (MOS) or, in general, conductor-insulator-semiconductor (CIS) devices are used exclusively as examples in this specification. Other types of solid-state and semiconductor circuit devices are also useful. Specifically, electro optical, superconductor, magnetic, ferro electric memory, electrooptomagnetic, and other solid-state devices can also be designed according to principles of this invention.
The “heart” of the transistor is the gate dielectric, where most electronic actions and the associated device heating or degradations occur. The gate oxide is the smallest but a critical feature of the transistor. It lies between the transistor's gate electrode, which turns current flow, and the silicon channel through which the current flows. The gate oxide insulates and protects the channel from the gate electrode preventing short circuits. Shrinking this oxide layer allows more current out of the switch with less voltage. More than any other part of the structure, this layer determines the device performance and reliability. Many think that this insulating layer would be the limiting factor for producing increasingly smaller chips.
The thickness of gate oxides is the subject of intense research. Bell Laboratory scientists have created a 5-atom silicon dioxide layer that included a 1-atom transition layer between this layer and substrate. A rapid thermal oxidation technique was used using pure oxygen at 1,000 C. for 10 seconds. Oxides less than 6 angstroms or 3 atoms have been made, but the leakage current was not manageable. Additional reliability issues included adhesion loss, texture, thermally or mechanically induced cracking, moisture adsorption, step coverage, and time-dependent behavior such as thermal conductivity, and breakdown voltage. The reduced mechanical strength is critical in both packaging and processing such as during chemical-mechanical polishing.
Traditionally, the gate dielectric is a thermally grown layer of silicon dioxide (SiO2) layer averaged about 25 atoms thick. By continually reducing the gate oxide thickness and the length of the gate electrode, the semiconductor industry has doubled the transistor's switching speed every 18 to 24 months according to the Moores Law. This has worked remarkably well, but problems exist. One is that the oxide often permits boron penetration from the gate into the threshold region, degrading the threshold voltage and device performance. The other problem is that, as device size shrinks, the gate oxide becomes so thin that tunneling currents arise from the gate through the oxide to the substrate, again degrading the device performance.
To overcome the first problem, transistor engineers have developed solutions involving stacked gates and various nitridation techniques. Nitradation adds nitrogen to the silicon dioxide. A successful two-step oxidation
itridation approach using a sequential in situ steam generation and rapid plasma nitridation process shows a 5-7 times reduction in current leakage compared to SiO2 at an effective oxide thickness of less than 20 A (or Angstroms).
The second problem relates to current tunneling through very thin oxide. This problem is more difficult and thought to require a change of materials. The tunneling current rises very quickly as the oxide is thinned down. It is believed that below about 14-15 A, new material must be used to replace the silicon dioxide. One would look for a thinner but defect-free SiO2 film to avoid the excessive leakage current. The new high-k materials must be put in place as the
14
-
15
A SiO2 layers. Some solutions are possible, but none fit all needs.
The new insulating material must also have the right dielectric constant and be chemically compatible with silicon to get the right interface. Interface remains a critical and largely unknown area of research. Interface microengineering may in fact be the key factor that will allow the new or old materials to continue the scaling of field-effect transistors (FET).
The defect-free gate dielectric layer must be put down uniformly in a thin film to tolerate subsequent silicon processing and temperature cycling. There is still no suitable high dielectric constant material and interface layer with the stability and interface cha

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