Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2000-06-15
2003-03-18
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
Reexamination Certificate
active
06535969
ABSTRACT:
BACKGROUND
The present invention relates generally to a method and system for managing the dynamic allocation and freeing of memory during program execution in electronic systems.
In general purpose electronic computer systems, most compilers typically provide a standard set of library functions that allocate and free memory. The provided libraries are given a starting address and region size based upon the operating system being used to execute the program. In an embedded system such as an Advanced Reduced Instruction Set Computer System (RISC) Machine (ARM) based system with no operating system defined at compile time, these library functions are not available. Thus, there lies a need for a method and system that is capable of allocating and freeing memory where library functions to implement such routines are unavailable. Furthermore, it is desirable to provide a method for allocating and freeing memory in systems without requiring intervention by the operating system even where the library functions may be available.
SUMMARY
The present invention is directed to a method and system for allocating and freeing memory in an electronic system. In one embodiment of the present invention, the method and system implement a step and structure for receiving a request to allocate a requested segment of available memory, a step and structure for searching for a free portion in the available memory, the free portion being sufficient to accommodate the requested segment, upon finding a free portion, a step and structure for creating a new segment in the free portion, the new segment including an allocated segment equal in size to the requested segment and further including a segment area that accommodates at least one flag of the allocated segment, the segment area being adjacent to the allocated segment, and a step and structure for setting the flag of the allocated segment.
REFERENCES:
patent: 5675790 (1997-10-01), Walls
Walker, “Butter Allocation Routines”, Jul. 1972.*
Walker, “The BGET Memory Allocator”, Aug. 21, 1996.*
Knowlton, “A Fast Storage Allocator”, 10/65, p.623-625, ACM vol. 8 No. 10.
Ellis Kevin L.
LSI Logic Corporation
Suiter & Associates PC
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