Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-31
2003-03-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06539519
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to a spatial characteristic and logical hierarchy based approach to compactly storing IC design data that reduces storage requirement and improves the efficiency of various common design operations.
2. Background Information
Over the years, with advances in process technology, the designs of integrated circuits (IC) have become increasingly complex. Long ago, IC designers turned to EDA tools to assist them in coping with the complexity of designing an IC, from design specification, synthesis, place and route, layout to verification (simulation and/or emulation). Recently, advances in process technology have made it possible to have ICs with multi-million transistors. The volume of data it takes to represent one of these IC designs has become so large, that it is a challenge for even the most powerful workstations to deliver reasonable performance (e.g. response time) for the IC designer. Even for workstations with very large amount of memory, capable of keeping most if not all of the IC design data in memory, it is still not uncommon to wait minutes if not hours for even some of the very basic operations to complete, e.g. like displaying a subset of an IC design, or searching for an element nearest to a target point, and so forth.
This trend of ever increasing complexity, and therefore larger and larger volume of design data to be stored and processed, is expected to continue without abatement. Thus, what is needed is an improved approach to storing IC design data, in particular, one that can reduce the storage requirement as well as be instrumental in improving the efficiency of various design operations, is desired.
SUMMARY OF THE INVENTION
In accordance with the present invention, descriptive data and truncated spatial data associated with elements of an IC design are stored into storage locations, employing a spatial characteristic and logical hierarchy based storage approach. The approach advantageously reduces the amount of storage locations required to store the IC design. To store the descriptive data and the truncated spatial data associated with an element, a position in the logical hierarchy for the element is first determined, using spatial data of the element. The descriptive and truncated spatial data of the element (less the spatial data that can be inferred from the storage position) are then stored into the storage locations, based at least in part on the result of the determination. As a result, storage requirement for descriptive and spatial data of IC elements is advantageously reduced. The spatial characteristic and logical hierarchy based storage approach also advantageously facilitates efficient successive accesses to retrieve the stored descriptive and truncated spatial data of a selected one or selected ones of the elements for an operation. In various embodiments, the operation may include but not limited to displaying a portion of the IC design, searching for an element closest to a target point, extracting connectivity for a portion of the IC design, and isolating a short in the IC design.
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Lauzon et al., “Two-Dimensional Run-Encoding for Quadtree Representation,” Computer Vision Graphics and Image Processing, Academic Press, Duluth, MA, US, vol. 30, No. 1, Apr. 1, 1985, pp. 56-69.
Garbowski Leigh Marie
Schwabe Williamson & Wyatt P.C.
Smith Matthew
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