Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-08-21
2003-05-13
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C324S1540PB, C209S574000
Reexamination Certificate
active
06563331
ABSTRACT:
This application is related to Korean patent application No. 97-12256 filed on Apr. 2, 1997 entitled “Method for Generating Lot in Semiconductor Test Process System” which is herein incorporated by reference for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an apparatus and method for testing semiconductor devices. More particularly, the present invention relates to a test and burn-in apparatus for semiconductor chip package devices, an in-line system which includes the test and burn-in apparatus, and a test method which employs the in-line system.
2. Description of the Related Art
A manufacturing process for producing semiconductor devices generally includes three sub-processes: a wafer fabrication process; a package assembly process; and a back-end process. The wafer fabrication process encompasses the procedures for creating a large number of circuits on a thin disc, or wafer, of semiconductor material such as silicon. The package assembly process is the process by which an individual chip, having been separated from the wafer, is assembled into a package for establishing interconnections with a suitable operating environment. The back-end process includes several test steps where the packaged devices are tested to determine the parameters of the devices and whether the devices appropriately perform their intended function. The back-end process also includes sort steps in which the tested devices are sorted according to their individual parameters.
FIG. 1
is a flow chart illustrating a conventional back-end process
80
for manufacturing semiconductor devices
89
. As shown in
FIG. 1
, the conventional back-end process
80
includes four test steps
81
,
82
,
83
and
84
, three associated sort steps
91
,
92
and
93
, a marking step
85
, a visual inspection step
86
, a packing step
87
, and a stocking step
88
. The four test steps are performed in sequence and include a DC test
81
, a burn-in step
82
, a room/cold test
83
, and a hot sort test
84
.
The assembled semiconductor devices
89
are provided to the back-end process
80
in package form. Specifically, the assembled semiconductor devices
89
are loaded in a device tray and then provided to the DC test
81
. The DC test
81
is performed to detect electrical failures which can occur during the package assembly process. After performance of the DC test
81
, the first sort step
91
is engaged during which good devices in the device tray are transferred to a burn-in board, while failed devices are scrapped. The burn-in board, once supplied with the good devices, is transferred to the burn-in step
82
.
The burn-in step
82
is an unusual test in which the semiconductor devices are subjected to extreme conditions (such as high temperature) in order to pre-screen out early device failures that might take place during actual usage. Following the burn-in step
82
, the burn-in board is returned to the first sort step
91
. The devices in the burn-in board are then sorted depending on the results of the burn-in step
82
. The passing devices are again loaded in the device tray and transferred to the next test step. Although, for clarity, the first sort step
91
appears as single block in
FIG. 1
, several processes are actually carried out during this step. Specifically, these processes include: moving the semiconductor devices from the device tray to the burn-in board and from the burn-in board back to the device tray; scrapping the failed devices after the DC test
81
; and sorting the devices after the burn-in step
82
. In most cases, both the first sort step
91
and the DC test
81
are carried out at the same stage of the manufacturing process.
Following the burn-in step
82
, the room/cold test
83
is performed. The room/cold test
83
begins after the good devices stored in the device tray are transferred to a room/cold tester. The room/cold tester includes a handler which shifts the devices from the device tray to a test tray. The room/cold test
83
is carried out at either about 25° C. (room temperature) or below 0° C. (freezing), so that DC failures or function failures can be checked. As the room/cold test
83
operation is completed, the devices in the test tray are again sorted, this time based on the room/cold test results. The good devices are shifted to the device tray which will carry the devices to the next test step while the failed devices are scrapped. The second sort step
92
is carried out by the handler of the room/cold tester. As described above, the test tray of the room/cold tester is used to carry the devices to and from the contact parts of the tester, while the device tray carries the devices between two testers.
The good devices in the device tray, having been room/cold tested, are then transferred to the hot sort test
84
, which is performed under high temperature conditions, i.e., approaching about 83° C. The hot sort test
84
, as is widely known in the art, verifies the electrical or functional characteristics of the devices and determines their operational speed. Similar to the room/cold test
83
, the hot sort test
84
includes the additional steps of removing the devices from the device tray and placing them in the test tray, and then removing them from the test tray and placing them on the device tray. Moving the devices from tray to tray is carried out by a handler (that is, by handling equipment) of the tester. The third sort step
93
is associated with the hot sort test
84
and is performed together with the shifting of the devices by the handler after completion of the hot sort test
84
.
When new semiconductor material arrives to be tested in the back-end process, it is handled by lot ID number. A human operator typically needs to input the lot ID number into the system in order to generate a test result and to measure the output obtained from a given input. Between the loading and unloading of the semiconductor devices, there are several general steps which take place inside the handler regardless of the test function being performed. These general steps require time to perform. Specifically, test tray index time, soaking hot or cold temperature processing time and sorting time must all be included in the overall device loading/unloading time during transfer between trays. The time requirements are even worse when rework is required following the main process. The total processing time includes a lot of preparation time during handler processing, even before actually testing the devices and combining the output. Additionally, a human operator has to count the total output and record the test results on every lot traveller card.
Unfortunately, as indicated above, conventional testers require additional equipment for transporting between test steps and transferring between trays (handling) both the devices to be tested and those which have already been tested. Furthermore, shifting the devices between trays during every test step adds time and complexity but does not add any value in the performance of the tests. In other words, the complicated processes engaged in by the handler have no positive affects on the performance of the tests. In fact, the conventional handling requirements add cost and complexity to the semiconductor device manufacturing process without any corresponding benefits. Specifically, the prior art handlers increase significantly the space and time requirements for moving the devices through the back-end process, as well as the costs associated due to increased equipment requirements. Also, semiconductor devices being manipulated by the handler are faced with the possibility of considerable damage during movement between trays.
Another significant problem in the prior art is that the current burn-in testers require a long test time. The excessive test time is further compounded by the amount of time it takes to transfer the devices between the burn-in board and the device tray, the time it takes to load and unload the burn-in board, and the time it takes to raise or dro
Cuneo Kamand
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Tang Minh N.
LandOfFree
Test and burn-in apparatus, in-line system using the test... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test and burn-in apparatus, in-line system using the test..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test and burn-in apparatus, in-line system using the test... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3034232