Message translation and data proxy service for remote data...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering

Reexamination Certificate

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Reexamination Certificate

active

06529972

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an interface protocol for use throughout computer networks to provide remote access for a component to memory elements that may not be members of the component's universal memory space.
Modern computer networks are populated by a number of different network components such as terminals, servers and peripheral devices. Consider a server
100
as shown in FIG.
1
. As shown, the server
100
may be populated by one or more central processing units (“CPUs”)
110
-
1
through
110
-N, a memory controller
120
, system memory
130
, on I/O bridge
140
and a plurality of 1/0 150-170 devices. Each of the input/output devices
150
,
170
may be so-called “intelligent peripherals” including an IO processor (“IOP”)
152
,
162
,
172
and peripheral components
154
,
164
,
174
.
Such modern networks increasingly are providing peripheral devices as adjuncts to a computer network, not as adjuncts to individual components. Thus, a server
100
may communicate with additional peripherals
191
,
192
,
193
via a “network fabric”
180
. As used herein, “network fabric” refers to network components (not shown) that may facilitate communication between two components of a computer network. Each of the additional peripherals
191
,
192
,
193
may include its own IOP
194
,
195
,
196
.
IOPs are advantageous for use in computer networks because they reduce the processing load of CPUs. Prior to the advent of IOPs, CPUs managed incremental operation of peripheral devices. IOPs now manage these functions when commanded by a CPU. Thus, if a disk drive
160
were commanded to write to disk a predetermined amount of data from system memory
130
, a CPU (say,
110
-
1
) need only issue a write command to the IOP
162
identifying the location and size of the data to be written to disk. Thereafter, the IOP
162
issues bus transactions and other control commands to cause the data to be furnished from the memory
130
. It retrieves the data from the memory
130
via the memory controller
140
and causes it to be written to disk. When all the data is stored to disk, the IOP
162
typically communicates with the CPU
110
identifying that the command has been completed. In this sense, the operation of servers is well-known. Further, network communication protocols are known for such purposes, such as the Intelligent I/O (I
2
O) Architecture Specification, Version 1.5 (March 1997) (available, as of the date of this writing, at http://www.i2osig.org/Architecture).
Performing data exchange across computer networks raises a new set of challenges. Computer networks are migrating toward a more distributed architecture in which peripheral devices possess local address spaces—they cannot gain direct access to the memory spaces of the hosts that may call them to perform I/O events. For example, a host
100
may communicate with a remote peripheral device
190
via the communication fabric
180
. Accordingly, there is a need in the art for a communication protocol that provides for communication with intelligent peripherals that use a different address space than a requesting agent.
SUMMARY
Embodiments of the present invention provide a message translation method in which a message is determined as being a request message or a reply message. For a request message, a proxy data buffer is allocated and address information in the request message is changed to refer to the proxy data buffer.


REFERENCES:
patent: 5113502 (1992-05-01), Merrill et al.
patent: 5195089 (1993-03-01), Sindhu et al.
patent: 5497480 (1996-03-01), Hayes et al.
patent: 5613071 (1997-03-01), Rankin et al.
patent: 5632016 (1997-05-01), Hoch et al.
patent: 6021464 (2000-02-01), Yao et al.
patent: 6347337 (2002-02-01), Shah et al.
Virtual Interface Architecture Specification, Version 1.0 (Dec. 16, 1997), at http://www.viarch.org.
Intelligent I/O (I2O) Architecture Specification, Version 1.5 (Mar., 1997), at http://www.i2osig.org/Architecture.

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