Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-11
2003-01-14
Siek, Vuthe (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06507942
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and circuits for measuring dimension uniformity of device features on integrated circuits.
BACKGROUND
Most integrated circuits (ICs) are built up using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete circuit. The patterning process, known as photolithography, defines the dimensions of the circuit features.
The minimum dimension that a given photolithography process can resolve is alternatively called the line width, the minimum feature size, or the critical dimension. The critical dimension is a very important parameter, as reductions in the critical dimension tend to improve speed performance.
FIG. 1
(prior art) is a cross-section of an MOS transistor
100
formed in the surface of a semiconductor substrate
102
. Transistor
100
conventionally includes source and drain regions
105
separated by a channel region
110
. A gate
115
and gate insulator
117
disposed over substrate
102
mask substrate
102
during formation of source and drain regions
105
; thus, the width of gate
115
defines the channel length L. It is generally desirable that transistor channel length be as short as practical to achieve maximum transistor switching speed. Thus, the length of gate
115
is typically the critical dimension. Other device features, such as conductor widths, are also defined to be the critical dimension.
The critical dimension of device features on various regions of an integrated circuit should be similar; otherwise, different regions of the IC will exhibit different speed performance, potentially leading to timing errors and other failures. Thus, critical dimensions are routinely measured on various parts of an IC as part of a comprehensive quality-control program.
Several conventional critical dimension measuring techniques allow IC manufacturers to verify critical dimension uniformity. In typical methods, an operator measures the critical dimensions of device features in a number of regions of an IC using a secondary electron microscope (SEM). Unfortunately, critical dimension measurement must only be done at selected portions of the IC, and cannot give precise information about performance of the device. Therefore, a technique is needed to determine the full range of performance values for the IC and to point out which portions of the IC have the best and worst performance.
Programmable logic devices (PLDs) are a well-known type of IC that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). The CLBs include memory arrays that can be configured either as look-up tables (LUTs) that perform specific logic functions or as random-access memory (RAM). Some modern FPGAs also include embedded blocks of RAM optimized for memory applications. Configuration data loaded into internal configuration memory cells on the FPGA define the operation of the FPGA by determining how the CLBs, interconnections, block RAM, and IOBs are configured.
Each element in a signal path introduces some delay. In FPGAS, the many potential combinations of delay-inducing elements complicate timing issues. FPGA manufacturers would like to guarantee the highest speed performance possible without causing ICs to fail to meet the guaranteed timing specifications. Unpredictable speed variations, including those associated with non-uniform critical dimensions, necessitate the use of undesirably large guard bands to ensure correct device performance. Thus, the need for a simple, inexpensive method for measuring the critical dimension uniformity is particularly important for FPGAS.
SUMMARY
Systems and methods are described for measuring the size uniformity of circuit features defined by an integrated-circuit (IC) fabrication process. In accordance with the inventive method, an IC is configured to include a number of substantially identical oscillators, each occupying a region of the IC. Each oscillator oscillates at a frequency that depends, in part, on the critical dimensions of features in the region in which it is formed. Consequently, the critical dimensions of regions across the surface of the integrated circuit can be mapped and compared by measuring the oscillation frequencies of the oscillators formed in those regions.
The oscillators can be implemented using programmable logic resources in embodiments of the invention applied to PLDS. In other embodiments, small, simple oscillators can be placed at various locations on the IC. Small ring oscillators can be formed in scribe lines, for example.
This summary does not define the invention: the invention is defined instead by the claims.
REFERENCES:
patent: 6182206 (2001-01-01), Baxter
patent: 6298453 (2001-10-01), Culbertson et al.
“The Programmable Logic Data Book 1999”; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124; pp. 3-3 to 3-22.
Calderone Anthony P.
La Tho Le
Wang Feng
Behiel Arthur J.
Levin Naum
Siek Vuthe
Xilinx , Inc.
Young Edel M.
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