Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-14
2003-01-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06510549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device, and more particularly, to a method of designing an ASIC type semiconductor integrated circuit device.
2. Description of the Related Art
A serial interface is a system for transferring data between LSIs at high speed with a reduced number of cables. For example, as shown in
FIG. 1
, the serial interface is mounted on an LSI to interconnect functional blocks such as a PLL (Phase Locked Loop) circuit
1
, a transmitting section
2
, and a receiving section
3
.
The PLL circuit
1
inputs a differential clock signal
1
a
of 125 MHz which is supplied from outside the LSI and increases the differential clock signal
1
a
to 10 times in frequency to output the 1.25-GHz clock signal
4
. At the same time, the PLL circuit
1
outputs the 125-MHz clock signal
5
. These clock signals
4
and
5
are supplied to the transmitting section
2
and the receiving section
3
through clock buffers
6
. The receiving section
3
inputs a differential serial data signal
3
a
of 1.25 Gbps and outputs a 10-bit parallel data signal of 125 Mbps. Also, the transmitting section
2
inputs the 10-bit parallel data signal
3
c
of 125 Mbps and outputs a differential serial data signal
3
d
of 1.25 Gbps.
Next, the operation of the transmitting section and receiving section will be described below in detail.
First, the structure and operation of the transmitting section
2
will be described.
Referring to
FIG. 2
, the transmitting section
2
is composed of a 10:1 MUX circuit. The transmitting section
2
is provided with a register
7
composed of flip-flop (F/F) circuits
9
, and a shift register
8
composed of flip-flop circuits
10
and selectors
11
.
In the transmitting section
2
, data
0
to data
9
of 10-bit parallel data
3
c
are taken in by the register
7
in response to a clock signal
5
of 125 MHz. After that, the data
0
to the data
9
are transferred from the register
7
to the shift register
8
based on the clock signal
4
of 1.25 GHz and a selection signal
8
a.
In this way, a serial data sequence
3
d
of 10 bits is obtained.
Next, the structure and operation of receiving section
3
will be described.
As shown in
FIG. 3
, the receiving section
3
is composed of a 1:10 demultiplexing (DEMUX) circuit with a clock recovery circuit block
12
added. The clock recovery circuit block
12
monitors the switching edge of the received data signal
3
a
of 1.25 Gbps to generate the 1.25-GHz clock signal with an optimal phase. Thus, the retiming of the received data is carried out. At this time, generally, the clock signal
4
of 1.25 GHz generated by the above mentioned PLL circuit
1
is supplied to the clock recovery circuit block
12
as a reference signal.
In the demultiplexing circuit, the 1.25 Gbps serial data
3
a
is taken in the shift register
14
in response to a clock signal
13
, and then is taken in a register
16
in response to a 125-MHz clock signal
15
. Then, the serial data is outputted as the parallel data
3
b
of 125 Mbps. A frequency divider
14
a
divides the 1.25-GHz clock signal
13
in frequency to {fraction (1/10)} to generate the 125-MHz clock signal
15
. The reference numerals
17
and
18
are flip-flop circuits of the shift register
14
and register
16
, respectively.
The serial interface for one channel is realized for the above mentioned PLL circuit
1
, transmitting section
2
, and the receiving section
3
to handle transmission data and reception data. However, actually, the serial interfaces for a plurality of channels are often provided for a single LSI.
As shown in
FIG. 4
, in order to realize this, the circuits such as the PLL circuit
1
are generally common to receiving section/transmitting sections (transmitting section
2
and receiving section
3
) for all channels
101
. Because the receiving section/transmitting section
101
must be reliably operated for all the channels, the input condition of the clock signals
4
and
5
to the receiving section/transmitting section
101
for the respective channels must be uniformly kept. Therefore, in such a structure, the distribution of the clock signals
4
and
5
from PLL circuit
1
to the receiving section/transmitting sections
101
is important. For this purpose, it is necessary to use a carefully designed clock tree
102
.
The clock tree
102
is formed by connecting buffers
6
of a plurality of stages. In this case, wiring line lengths between the stages are made equal to each other, and the structures of paths of the clock tree are made equal to each other so that a clock skew can be reduced.
Therefore, in a conventional ASIC (Application Specific Integrated Circuit) which includes a serial interface circuit, as shown in
FIG. 4
, the receiving section/transmitting sections
101
and the PLL circuit
1
are described in an ASIC design data base as independent macros. The clock tree
102
is designed specifically for every kind of macro, to connect between them. Also, a wiring line structure for the exclusive use is designed for every kind of macro in case that the circuit which needs a power supply circuit is used for the receiving section/transmitting sections. Also, the wiring line structure for the exclusive use is designed in case that a signal is communicated from the receiving section/transmitting sections to a common section.
When the serial data interface circuit is mounted on the conventional ASIC system semiconductor integrated circuit device as mentioned above, it is necessary to carefully design the semiconductor integrated circuit device for every kind of macro, resulting in a long design turn-around time, and lack in the uniformity of the design quality.
An integrated circuit device is described in Japanese Laid Open Patent Application (JP-A-Showa 60-1845: first conventional example). In this reference, the occupation area of a single chip for a circuit layout pattern having a function has an overlapping shape through a symmetrical conversion.
A method of forming a master slice type integrated circuit device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-24763: second conventional example). In this reference, a wiring line layout pattern to a pair of function blocks is formed in a point symmetry or in a mirror symmetry. Each of the function blocks is composed of at least one basic cell and the function blocks have the same circuit structure. According to the conventional example, the input/output pin positions of each of the logical function blocks can be arranged in symmetrical positions. Also, the unevenness of the wiring line length which is caused by the position relation of the input/output pins is eliminated. Moreover, when it is requested that the wiring line lengths between the respective logical function blocks are made equal to each other for the parallel processing of a plurality of signals, the influence of the input/output pin position of each logical function block is removed. The unevenness of the wiring line length which is caused by the position relation of the input/output pins is eliminated.
In Japanese Laid Open Patent Application (JP-A-Heisei 4-372169: a third conventional example), a master slice LSI can be obtained. In this reference, a macro cell is composed of terminals which are in the same positions, the same number of basic cells, and a delay element provided between the input terminal and the output terminal on a signal propagation route and having one of a plurality of delay values. Therefore, one macro cell can be easily replaced by another macro cell having the desired delay value. Also, it is not necessary to insert a new delay element once again by carrying out the design again. In addition, a timing error, can be easily eliminated.
In Japanese Laid Open Patent Application (JP-A-Heisei 5-29459: a fourth conventional example), it is described that when a semiconductor substrate area is divided into a plurality of regions for a process of forming wiring li
Hayes & Soloway P.C.
NEC Corporation
Siek Vuthe
Thompson A. M.
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