Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-10
2003-09-09
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S623000, C438S125000, C257S700000, C257S701000, C257S702000, C257S703000, C257S773000, C257S774000, C257S758000, C029S825000, C029S829000, C029S830000
Reexamination Certificate
active
06617243
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to multilayer ceramic substrate carriers with routing that reduces via depth and avoids via-bulge.
BACKGROUND OF THE INVENTION
Controlled collapse chip connection (C
4
) or flip-chip technology has been successfully used for over twenty years for interconnecting high I/O (input/output) count and area array solder bumps on silicon chips to base ceramic chip carriers, for example alumina carriers. In C
4
technology or flip chip packaging, one or more integrated circuit chips are mounted above a single or multiple layer ceramic (MLC) substrate or board, and pads on the chip(s) are electrically or mechanically connected to corresponding pads on the other substrate by a plurality of electrical connections, such as solder bumps.
In MLC packages, a ceramic substrate is the platform upon which chips, passive components, protective lids, and thermal enhancement hardware are attached according to well known techniques. Wiring patterns within the substrate carrier define escape paths in single chip modules (SCMs) and multichip modules (MCMs), transforming the tight I/O pitch at the die level of the chips to a workable pitch at the board level. The wiring pattern also establishes the modules' power distribution network. Vertical metal vias provide interconnections between the various layers within the MLC. C
4
pads can be directly soldered onto MLC vias, providing low inductance, direct feed to power and ground planes.
Planarity of the chip attach surface of substrates/carriers is important in order to reliably mount chips via the C
4
process to their carriers. One aspect contributing to the non uniformity of the carrier surface is related to a condition referred to as via-bulge. During firing, the expansion/contraction of the typical conductive paste is not the same as that for the typical dielectric material encompassing the vias and etch lines. Therefore, vias which protrude from the surface and that go into the substrate through many layers will tend to form hills on the carrier's mounting surface, i.e., will produce via-bulge.
Accordingly, what is needed is an approach to routing signal lines that substantially eliminates excessive via depth for high C
4
density MLC substrates. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides aspects for routing in multilayer ceramic substrates that reduces via depth and avoids via bulge. The aspects include providing a multilayer ceramic substrate with at least two redistribution layers. Vias for each of a plurality of signal lines are jogged on at least a second redistribution layer of the at least two redistribution layers. Further, the aspects include providing the second redistribution layer no more than seven layers deep in the multilayer ceramic substrate.
With the present invention, the ability to increase signal density on chips interfacing to ceramic substrates without causing problems with planarity of the mounting surface is achieved by limiting the depth of vias which go to the chip mounting surface of the substrate. In addition, through the present invention, substrate designs, which have had to move to either a higher cost substrate dielectric, and/or to a tighter C
4
/via pitch, are able to be produced with reduced cost. Further, the present invention allows for about a ⅓ increase in signal density, while still maintaining a high power to signal ratio as compared to a typical interstitial C
4
pattern. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.
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patent: 5302219 (1994-04-01), Hargis
patent: 5861670 (1999-01-01), Akasaki
patent: 5914533 (1999-06-01), Frech et al.
patent: 5946552 (1999-08-01), Bird et al.
patent: 6021564 (2000-02-01), Hanson
patent: 6341417 (2002-01-01), Gupta et al.
U. Ghoshal, Static ZT-Meter for Screening TE Samples, 2 pages.
International Business Machines - Corporation
Loke Steven
Parekh Nitin
Sawyer Law Group LLP
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