Standard block architecture for integrated circuit design

Details Standard block architecture for integrated circuit design Standard block architecture for integrated circuit design

2000-03-14

2003-03-18

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06536028

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to semiconductor design process and, particularly, to integrated circuit (IC) design process including electronic design automation (EDA) and automated IC design tools.
2. Background Art
Modern IC design process depends on a highly developed software technology directed to optimizing IC density, timing, and other electrical parameters in order to achieve low cost, improved performance, and high reliability while reducing overall design turn-around-time. It is common to find computer-aided IC design tools (also known as CAD tools and EDA tools, hereafter collectively “IC design tools”) that are utilized for the design of complex ICs with millions of components. To deal with such complexity, IC design tools must have the capacity to process millions of gates, must be computationally fast, and must produce optimal results in order to reduce the number of iterations in the design flow (See
FIG. 1
for a typical IC design flow). In other words, IC design tools must keep pace with the rapidly increasing complexity as outlined by Moore's Law. (Moore's Law predicted that the design complexity and speed of ICs will double every two (2) years); See
FIG. 2
for a Semiconductor Industry Association's (SIA's) projection of IC complexity development along with the increased importance of deep-submicron (DSM) for physical design.
Over time there have been many generations of IC design tools for handling the increasing number of components (e.g., gates) on a single chip. The increasing IC complexity overtime resulted in the evolution of IC design methods including adoption of higher levels of abstraction as illustrated in FIG.
3
.
FIG. 3
, shows the evolution over time of ICs, from small ICs comprised of transistors (or polygons) to larger ICs comprised of higher levels of abstraction such as gates, (or cells), and blocks.
Early on, with a relatively small number of gates, logic design with transistors and physical design with polygons
30
in an IC
40
was performed manually. With the emergence of synthesis and placement and routing (P&R) tools, gates and standard cells
32
have been introduced as a basic architectural feature for the design and implementation of ICs. As a result, the physical design and implementation of ICs was automated using the standard-cell-based architecture
42
. Physical design tools, particularly, automated physical design tools, have long been key in implementing the IC design evolution. In general, physical design of an IC is the process of converting electrical circuit specifications into an IC layout. Physical design requires exacting details about components, geometric patterns and geometric rules, such as separation, spacing, etc. Physical design automation tools use algorithms and data structures to achieve optimal arrangement of components and efficient interconnection between components to obtain the desired functionality. However, unlike front-end design tools (e.g., logic design tools), physical design tools have not kept pace with the IC evolution. Physical design tools for both flat standard-cell-based and functional-block-based architectures
42
and
44
are inadequate and have not kept pace with large scale ICs design. For example, automatic P&R tools for implementing ICs with a flat cell-based architecture
42
are reaching practical limits in the number of cells they can process automatically; and P&R tools for implementing ICs with a functional block-based architecture
44
are less automatic thus consuming more designer resources.
The development of functional block-based architecture
44
, came into existence with the evolution of synthesis tools that gave rise to Register Transfer Level (RTL) design. RTL was introduced to specify the IC functionality design with a behavior-level specification. Behavioral and RTL specifications can be coded in any currently available hardware description language (HDL). From RTL, gate level information can be generated by logic synthesis tools, and this information (commonly referred to as the “netlist”) can be used in generating layout including physical interconnections (wires) between the gates (which are provided as part of the netlist). The transition from gate-level to RTL-level methodologies in the front-end design tools accommodates the evolution of IC design, but the limitations in the back-end (e.g. physical) design tools have yet to be overcome. To better understand these limitations, an overview of the standard-cell-based and functional-block-based architectures and corresponding design methodologies are illustrated in
FIGS. 4 and 5
, respectively.
As shown in
FIG. 4
, standard cell architecture of an IC
42
considers the IC layout to be formed of rectangular cells
54
with a similar height, the so-called standard cells. The standard cell layout is inherently non-hierarchical, hence the term flat cell-based design. In this layout, cells
54
are placed in rows
52
with, or without, spaces (channels) therebetween. In a layout with channels (not shown), the channels are used to accommodate wires for cell interconnections. In a layout without channels, all interconnections are routed over the cells. In the standard-cell-based architecture
42
, each cell
54
is equivalent to a primitive component of the circuit embodied in the IC. The functionality of each cell is typically predefined and available from a cell library. After the logical design phase
14
(e.g., by high-level synthesis from behavioral description to RTL code followed by RTL synthesis to gate-level), the design process proceeds with the physical design phase
16
. The standard cell design style is relatively simple but has practical limitations for processing large ICs, primarily due to the fact that physical design deals with significantly more design elements than logic design. Also, long interconnects in large-scale standard cell layout typically leads to non-deterministic timing results or signal integrity issues. As a result, standard cell design optimization requires a repeat in a number of iterations of either one or both of the logical and physical design phases
14
and
16
(indicated by return arrows). For instance, engineering design change orders (ECOs) which introduce changes in the design (e.g., function, netlist, or timing) require a repeat of the standard cell design cycle. Moreover, although a cell-based approach is fairly automatic, substantial efforts and resources must be expended in large scale IC designs to maintain synchronization between the vast information generated, respectively, by the logical and physical design teams.
By comparison, in an IC with a functional block-based design architecture
44
, as shown in
FIG. 5
, the circuit embodied in the IC is partitioned (step
11
) into a hierarchy of functional blocks
62
. Each individual functional block can be implemented by being further partitioned into a hierarchy of sub-blocks, or by using a standard cell approach as described above. Each IC design team is typically responsible for the logical and physical design of a respective functional block. However, as the individual block designs progress there remains a challenge to synchronize tuning of the design requirements and related information among the individual design teams. A separate top-level design team must then assemble the functional blocks in an integration phase performed at a top-level of the hierarchy using floor planning (or chip assembly) tools. Reconciling mismatches between the functional blocks requires ECOs and is a significant challenge which floor planning tools cannot easily overcome with predictable results.
The difficulties associated with a functional block design style are due to the irregular sizes and diverse timing requirements of functional blocks
62
. Because the floor planning involves a multiple number of constraints (such as overall IC and blocks size, aspect ratio, timing, pin accessibility, etc.), optimizing the design with functional blocks, particularly with

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