Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-07-03
2003-05-06
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S042000, C714S057000, C714S723000, C382S145000, C382S147000, C382S149000, C324S754120
Reexamination Certificate
active
06560729
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to testing of IC (integrated circuit) dies during manufacture of IC (integrated circuit) packages, and more particularly, to a method and system for automatically determining and displaying the physical location of a failed cell of an array of memory cells on magnified images of a memory IC (integrated circuit) die having the array of memory cells.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a memory IC (integrated circuit) die has a memory device fabricated therein such as a non-volatile flash memory device comprised of an array of flash memory cells
20
, as known to one of ordinary skill in the art of electronics. In
FIG. 1
, a first flash memory cell
22
and a second flash memory cell
24
form a first row of flash memory cells, and a third flash memory cell
26
and a fourth flash memory cell
28
form a second row of flash memory cells. The first flash memory cell
22
and the third flash memory cell
26
form a first column of flash memory cells, and the second flash memory cell
24
and the fourth flash memory cell
28
form a second column of flash memory cells.
An array of memory cells for a typical non-volatile memory device has more numerous flash memory cells (such as millions of flash memory cells) with more numerous rows and columns of flash memory cells. However, four memory cells
22
,
24
,
26
, and
28
in an array of two rows by two columns are illustrated in
FIG. 1
for clarity of illustration.
Referring to
FIG. 2
, a cross sectional view
100
is shown of one of the flash memory cells
22
,
24
,
26
, and
28
. A flash memory cell is a floating gate MOS (metal oxide semiconductor) type of device for a non-volatile flash memory device, as known to one of ordinary skill in the art of electronics. The cross section
100
of a flash memory cell includes a control gate
102
which typically is comprised of polysilicon. A drain junction
104
that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within a semiconductor substrate
106
. A source junction
108
that is doped with the junction dopant is formed within the semiconductor substrate
106
.
A control dielectric structure is formed over a control gate area
110
within the semiconductor substrate
106
that is disposed between the drain junction
104
and the source junction
108
. The control dielectric structure is comprised of a stack of a first dielectric layer
112
disposed on the semiconductor substrate
106
, a second dielectric layer
114
disposed on the first dielectric layer
112
, and a third dielectric layer
116
disposed on the second dielectric layer
114
. In one example of the control dielectric structure, the first dielectric layer
112
is comprised of silicon dioxide (SiO
2
), the second dielectric layer
114
is comprised of silicon nitride (SiN), and the third dielectric layer
116
is comprised of silicon dioxide (SiO
2
). A first field oxide
118
is formed within the drain junction
104
, and a second field oxide
120
is formed within the source junction
108
for electrically isolating the gate dielectric structure comprised of the first, second, and third dielectric layers
112
,
114
, and
116
and the control gate
102
.
Referring to
FIGS. 1 and 2
, the drain junction of each of the memory cells in a column are coupled together to form a “bit-line”, as known to one of ordinary skill in the art of electronics. In
FIG. 1
, the first column of memory cells
22
and
26
are coupled to a first bit-line
32
, and the second column of memory cells
24
and
28
are coupled to a second bit-line
34
, for example. The control gate of each of the memory cells in a row are coupled together to form a “word-line”, as known to one of ordinary skill in the art of electronics. In
FIG. 1
, the first row of memory cells
22
and
24
are coupled to a first word-line
42
, and the second row of memory cells
26
and
28
are coupled to a second word-line
44
, for example.
Referring to
FIG. 2
, during a program operation or an erase operation of a cell of a flash memory device, charge carriers are injected into or injected out of the second dielectric layer
114
. Such variation of the amount of charge carriers within the second dielectric layer
114
alters the threshold voltage of the control gate
102
, as known to one of ordinary skill in the art of electronics. For example, when electrons are the charge carriers that are injected into the second dielectric layer
114
, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are injected out of the second dielectric layer
114
, the threshold voltage decreases.
The charge carriers are injected into or injected out of the second dielectric layer
114
from the drain junction
104
to the control dielectric structure when bias voltages are applied on the control gate
102
via a control gate terminal
122
(i.e., the word-line coupled to the control gate
102
), as known to one of ordinary skill in the art of electronics. For example, when a bias voltage of approximately +12V is applied on the control gate terminal
122
for programming the memory cell, electrons are injected into the second dielectric layer
114
from the drain junction
104
by hot carrier injection effect, as known to one of ordinary skill in the art of electronics. Alternatively, when a bias voltage of approximately −12V is applied on the control gate terminal
122
for erasing the memory cell, electrons are injected out of the second dielectric layer
114
and to the drain junction
104
by hot carrier injection effect, as known to one of ordinary skill in the art of electronics.
For reading digital bit information from a memory cell, a gate-to-source voltage of approximately 5.0V and a drain-to-source voltage of approximately 1.5V are applied to the memory cell. With such bias, the memory cell conducts current or does not conduct current depending on whether the memory cell has been programmed or erased. These two conditions are used as the two states for storing digital bit information within the flash memory cell
100
, as known to one of ordinary skill in the art of electronics.
During manufacture of a non-volatile flash memory device, the memory IC die for the non-volatile flash memory device is tested for proper functionality. Systems for testing the functionality of the memory IC dies are known to one of ordinary skill in the art of IC package manufacture. Such a testing system outputs label information of a failed memory cell that does not function properly during such testing for indicating the physical location of such a failed memory cell on the memory IC die.
Label information for a memory IC die is devised during layout of the integrated circuit of the memory IC die, and such label information is recorded in a design book, as known to one of ordinary skill in the art of integrated circuit design. For example, referring to
FIG. 3
, an array of memory cells are fabricated in a memory IC die
202
. The memory IC die
202
of
FIG. 3
includes a plurality of contact pads
204
,
206
,
208
,
210
,
212
,
214
,
216
,
218
,
220
, and
222
for providing connection to nodes of the flash memory integrated circuit fabricated on the IC die
202
. A typical memory IC die includes more numerous contact pads, but ten contact pads
204
,
206
,
208
,
210
,
212
,
214
,
216
,
218
,
220
, and
222
are illustrated in
FIG. 3
for clarity of illustration.
Further referring to
FIG. 3
, the array of memory cells are divided into a plurality of sectors, including a first sector
232
, a second sector
234
, a third sector
236
, and a fourth sector
238
, on the memory IC die
202
. A typical memory IC die includes more numerous sectors, but four sectors
232
,
234
,
236
, and
238
are illustrated in
FIG. 3
for clarity of illustration. The reason for designing the memory IC die
202
with a plurality of sectors is that during layout of the memory IC die
202
, the layout for each sector may
Anuntapong Suntra
Phurikhup Surasit
Soiluck Wannee
Choi Monica H.
Moise Emmanuel L.
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