Port prioritization scheme

Details Port prioritization scheme Port prioritization scheme

2000-03-30

2003-03-11

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S163000, C711S173000, C711S131000, C711S150000

Reexamination Certificate

active

06532524

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to dual port memories generally and, more particularly, to a method and/or architecture for port prioritization in dual port memories.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional asynchronous dual port memory
10
is shown. The dual port memory
10
generally comprises a comparator
12
, a comparator
14
, a read/write control block (or circuit)
16
, a read/write control block (or circuit)
18
, an arbiter circuit
20
and a core
22
.
In previous asynchronous designs, a complex arbitration scheme is used to eliminate memory cell crow bar current when both ports are attempting to write into the same memory cell location of the core
22
with opposite data (contention write). In previous synchronous dual port designs, potential memory cell crow bar current is not eliminated. Such a scenario increases current consumption (ICC) of the memory
10
. A conventional asynchronous dual port allows either port to take control of the memory when both ports are trying to store or retrieve data from the same memory location. The arbitration circuit assigns priority by selecting the port which is the first to request a memory access.
Conventional approaches for eliminating memory cell crow bar current have been implemented for asynchronous dual port designs by using arbitration schemes. Asynchronous dual port arbitration schemes require complex logic to determine port priority. Because arbitration logic is not implemented for conventional synchronous dual port designs, memory cell crow bar current is not eliminated. Memory cell crow bar current increases current consumption for synchronous dual port memories.
It may be desirable to provide a method to eliminate crow bar current and reduce ICC for synchronous dual port designs during a write access contention mode. It may also be desirable to provide a method for eliminating crow bar current in asynchronous dual port designs without requiring complex arbitration circuitry.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first compare circuit, a second compare circuit and a memory. The first compare circuit may be configured to present a first match signal in response to a first address and a second address. The second compare circuit may be configured to present a second match signal in response to the first match signal, a first write enable signal and a second write enable signal. The memory may also be configured to present the first and second write enable signals. In one example, the memory may be configured to store and retrieve data with zero waiting cycles in response to the second match signal.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) eliminate memory cell crow bar current without requiring complex arbitration circuitry, (ii) allow a prioritization scheme that may be implemented in either synchronous or asynchronous dual port memories, (iii) allow a high priority port to store or retrieve data at any memory location with zero waiting cycles, (iv) provide an address match signal if a user desires external arbitration to be implemented, (v) reduce user-defined arbitration logic, (vi) ensure a memory contains valid data during a write access contention mode without requiring additional arbitration circuitry, (vii) allow a user to select the high priority port which always obtains access to the memory, and/or (viii) allow write access to the high priority port, which may prevent unexpected data being written into the memory during the write contention mode.


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patent: 6345335 (2002-02-01), Flynn
Alves et al., “Built-In Self-Test for Multi-port RAMs”, © 1991, IEEE, p. 248-251.*
Crawford et al., “Cache Coherence in a Multiport Memory Environment”, © 1994 IEEE, p. 632-642.

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