Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-14
2003-09-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06622293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods and computer-aided-design devices for designing semiconductor integrated circuits, and particularly relates to a method and computer-aided-design devices for designing a wire layout of semiconductor integrated circuits.
2. Description of the Related Art
When manufacturing semiconductor devices, plasma exposure during a manufacturing process electrically charges up the wafer, and such electrical charge may result in damages to the gate-oxide layer of transistors. In order to avoid such damages caused by plasma exposure, an antenna check based on an antenna ratio needs to be performed at the time of semiconductor device design.
The antenna ratio is a ratio of a total combined area of all wires and vias to an area of a gate of current interest where these wires and vias are connected to the gate of current interest. The larger the ratio, i.e., the larger the total area of all the wires and vias relative to the gate, the greater the amount of charge built up per a unit area of the gate. This results in a greater risk of damage. At the time of design, therefore, a check needs to be made so as to restrict the antenna ratio to a value smaller than a certain limit.
When designing semiconductor devices, modules corresponding to functional blocks of a semiconductor-chip circuit are designed first, and, then, a wire layout is determined within each of the modules. Thereafter, wire layouts connecting the functional blocks together are decided between the modules.
The problem is that there may be a case in which a total area size of all wires connected to a cell input (gate) exceeds the maximum limit of a tolerable antenna ratio at the time of designing inter-module wire layouts even after wire layouts inside the modules are successfully designed without antenna errors. In such a case, it is necessary to go back to a design stage for designing layouts inside modules, resulting in an increase of processing time required for determining wire layouts. This problem will be described in detail in the following.
FIG. 1
is a plan view of a semiconductor device showing wire layouts inside as well as between modules.
FIG. 2
is a cross-sectional view of the semiconductor device of FIG.
1
.
In the semiconductor device of
FIG. 1
, a module
10
includes a cell-input portion
11
serving as an input node of a given cell (logic device) provided in the module
10
, a module terminal
12
, and wires L
1
through L
4
connecting between the cell-input portion
11
and the module terminal
12
. A module
13
includes a cell-output portion
14
serving as an output node of a given cell (logic device) provided in the module
13
, a module terminal
15
, and wires L
9
and L
10
connecting between the cell-output portion
14
and the module terminal
15
. As shown in
FIG. 1
, the module terminal
12
and the module terminal
15
are connected by inter-module wires L
5
through L
8
.
As shown in
FIG. 2
, the wires L
1
and L
3
are formed in a first metal layer
21
, and the wires L
2
, L
4
, L
5
, L
7
, and L
10
are formed in a second metal layer
22
. Further, the wire L
6
, L
8
, and L
9
are implemented in a third metal layer
23
. As can be seen by making a comparison with
FIG. 1
, the wires in the first metal layer
21
and the third metal layer
23
extend in a horizontal direction of
FIG. 1
, whereas the wires in the second metal layer
22
extend in a vertical direction of FIG.
1
. Further, the cell-input portion
11
is provided in a polysilicon layer
24
, and the cell-output portion
14
is formed in a diffusion layer
25
.
For the sake of explanation, layers are taken into consideration one after another from the first metal layer
21
to the third metal layer
23
from the bottom to the top. When the first metal layer
21
is taken into consideration, the wire L
1
is connected to the cell-input portion
11
. When the second metal layer
22
is taken into consideration, the wires L
2
, L
4
, and L
5
are connected to the cell-input portion
11
. At a time when the second metal layer
22
is formed during the manufacturing process, therefore, the cell-input portion
11
builds up electrical charge therein that is commensurate with a total area size of the wires L
1
, L
2
, L
3
, L
4
, and L
5
.
Let us assume that an antenna ratio of the cell-input portion
11
is within a tolerable range as far as the wires L
1
, L
2
, L
3
, and L
4
are concerned, but exceeds the maximum limit when the wire L
5
is added. In this case, even if the circuit is designed not to suffer an antenna error when the wires L
1
, L
2
, L
3
, and L
4
inside the module are laid out, addition of the inter-module wire L
5
results in an exit from the tolerable range. This results in damages to the cell-input portion
11
. In such a case, therefore, it is necessary to go back to a design stage for designing wire layouts inside modules, with a resulting increase in the processing time required for the wire layouts.
Accordingly, there is a need for a method and a computer-aided-design device for designing layouts efficiently while avoiding antenna error.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a method and a computer-aided-design device that substantially obviate one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a method and a computer-aided-design device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of determining wire layouts of a circuit in a semiconductor device that includes a plurality of modules each corresponding to a circuit block, the method including the steps of providing module terminals of modules to be connected together in a same single layer, determining layouts of wires connected to the module terminals inside the respective modules by laying out the wires in one or more layers no higher than the single layer, and determining layouts of inter-module wires connecting between the module terminals by laying out the inter-module wires in the one or more layers no higher than the single layer.
According to one aspect of the present invention, the method as described above further includes the steps of identifying a highest layer used in a first one of the modules if the first one of the modules has internal wire layouts thereof already determined in advance, and determining the layouts of wires connected to the module terminals inside a second one of the modules that is to be connected to the first one of the modules such that the wires reach a layer that is the same as said highest layer.
In the method as described above, terminals of modules are arranged in the same layer, and relevant wires inside the modules and inter-module wires are laid out in the layers no higher than the layer that includes the module terminals. When layers are formed successively from the bottom to the top in the manufacturing process, and the inter-module wires are connected to the module terminals in the end, a cell-input portion ends up being connected to a cell-output portion without an exception. This ensures that all electrical charge is discharged from the cell-output portion, thereby avoiding destruction of the cell as long as the wires inside the modules are laid out so as to avoid an antenna error. When a first module is to be connected to a second module th
Banno Koji
Osajima Toru
Suzuki Kenji
Lin Sun James
Staas & Halsey , LLP
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