Semiconductor memory device and fabrication thereof

Details Semiconductor memory device and fabrication thereof Semiconductor memory device and fabrication thereof

1998-09-16

2003-01-28

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S390000

Reexamination Certificate

active

06512277

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabrication thereof, and more particularly to a mask read-only memory (ROM) and a fabrication thereof.
2. Description of the Related Art
Mask ROMs can be classfied into NAND-type ROMs and NOR-type ROMs. It had been considered that NOR-type ROMs were superior in terms of operation speed, but difficult to shrink in size to meet high-density requirement for integrated circuit (IC) applications. A great advancement toward solution of this problem has been made in flat NOR-type ROMs by forming bit lines with diffusion to establish contact free electrical connection and by eliminating element separating regions in array configuration of memory cells.
Referring to
FIGS. 3
,
4
(
a
),
4
(
b
),
4
(
c
) and
4
(
d
), a fabrication process of a flat NOR-type mask ROM is described.
FIG. 3
is a schematic top plan view of an array configuration of memory cells of the flat NOP-type mask ROM. FIGS.
4
(
a
),
4
(
b
),
4
(
c
) and
4
(
d
) are cross sections taken through the line
4
—
4
of
FIG. 3
, illustrating fabrication process steps.
Viewing in
FIG. 3
, bit lines
6
of difusion region, of an N conductivity type formed in a silicon substrate of a P conductivity type extend in d vertical directior), and word lines
8
are disposed above and extend orthogonal to the direction of the bit lines
6
. The word lines
8
are made of a polycide structure that is a laminate structure of a lower polycrystailine silicon layer and an upper sullcide layer. Below each of the word lines
8
and between the adjacent two bit lines
6
is formed a channel of a memory cell transistor.
In fabrication, as shown in FIG.
4
(
a
), the surface of a silicon substrate
1
of P conductivity type is subjected to oxidation to grow oxides to form a pad oxide film
2
and a silicon nitride film
3
is deposited on the film
2
. The silicon nitride film
3
acts as an oxidatioin resisting film. A resist (photoresist)
4
is formed on the silicon nitride film
3
. The resist
4
has openings where diffusion regions of N conductivity, which act as bit lines, are to extend. The silicon nitride film
3
is selectively removed, as shown in FIG.
4
(
b
), by anisotropic etching technique with the resist
4
as a mask. Using the resist
4
as a mask, ion implantation is performed to introduce dopant of N conductivity type, such as arsenic (As), into the substrate
1
to form dopant implanted portions. In FIG.
4
(
c
), after the resist
4
has been removed, selective oxidation is performed with the silicon nitride film
3
as a mask. In the selective oxidation, the implanted dopant atoms are diffused to form dopant diffusion regions
6
of N conductivity and field oxide regions
5
are formed on the dopant diffusion regions
6
. These dopant diffusion regions
6
act as bit lines, respectively.
Referring to FIG.
4
(
d
), after removing the silicon nitride film
3
and pad oylde film
2
to expose surface portions of the silicon substrate
1
, gate oxide regions
7
are formed on the exposed surface portions of the silicon substrate
1
. Subsequently, a laminated structure of a lower polycrystalline silicon film and an upper tungsten suicide (WSi) film is deposited over the whole surface of the assembly, and patterned to define word lines
8
. Formed below each of the word lines
8
and between the adjacent two of the N conductivity-type diffusion regions
6
(bit lines) is a channel
9
.
Subsequently, an interlayer film is deposited, and a predetermined dopant of P conductivity such as boron (B) is introduced into the channel portion of each of the predetermined ones of the memory cell transistors through the interlayer film by ion implantation. After the step of writing information, wiring lines are formed to provide a flat NOR-type mask ROM having memory cell transistors, each having a channel length L and a channel width W.
In the conventional flat NOR-type mask ROMS, leaks between adjacent elements and punch-through between the source and drain (between diffusion regions of N conductivity type) tend to occur. Thus, it is difficult to reduce the minimum Lmin of the channel length of each memory cell transistors to a dimension sufficiently small enough to allow memory cells to shrink in size to meet high-density requirement for integrated circuit (IC) applications.
An object of the present invention is to improve a frat NOR-type mask ROM by suppressing leaks between the adjacent elements and punch-through between the source and drain. This reduces the minimum Lmin of the channel of a memory cell transistor to a dimension sufficiently small enough to allow memory cells to shrink in size to meet high-density requirement for integrated circuit (IC) applications.
SUMMARY OF THE INVENTION
The object is accomplished by ion implantation of dopant atoms that induce the same conductivity type as a semiconductor substrate. The implanted portions are produced around a predetermined projected range (Rp). The predetermined projected range is determined such that, in the subsequent thermal oxidation, the implanted dopant atoms are difused to produce dopant diffusion regions at boundaries between each channel and the adjacent two diffusion regions or the opposite conductivity type to the substrate.
The opposite conductivity type diffusion regions act as bit lines, respectively, and include other dopant atoms that have been introduced by ion implantation. Both of the ion implantation processes are performed using a resist layer as a common implantation mask.
Assuming now that a semiconductor substrate is of a P conductivity type, N conductivity-tyoe dopant atoms are introduced into the substrate to form first implanted portions and P conductivity-type dopant atoms, e.g. boron (a), are introduced to form second implanted portions. Using a resist layer as a common ion-implantation mask, an ion-implantation is performed to form the first implanted portions around a first projected range (Rp) and to form the second implanted portions around a second projected range (Rp) that is deeper than or equal to the first projected range. Boron has a larger diffusion coefficient than the N conductivity-type dopant atoms. In the subsequent thermal oxidation, the implanted boron atoms are distributed into P
+
conductivity-type diffusion regions that extend to define boundaries between a channel and the adjacent two of the N conductivity-type diffusion regions. The N conductivity-type diffusion regions act as bit lines, respectively,
This arrangement restrains depletion region from extending beyond each of the N conductivity-type diffusion regions, thus suppressing the occurrence of punch-through effect. This makes a great contribution to a reduction of the channel length of each memory cell transistor.
The P
+
conductivity-type diffusion regions act as a channel stop, thus suppressing leak between the adjacent elements.
Without using costly photolithography technique, the present invention relies on less costly ion implantation or the dopant atoms of the same conductivity type as a substrate to accomplish the suppression of occurrence of punch-through and the suppression of leak, thus minimizing a fabrication cost increase.
According to one aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, the method comprising the steps of:
providing a substrate of a first conductivity type;
forming a pad oxide film in said substrate and an oxidation resisting film on said pad oxide film;
forming a resist over the whole surface area of said oxidation resisting film, said resist having openings where bit lines are to extend;
selectively etching away said oxidation resisting film using said resist as a mask;
introducing, using said resist as a mask, a first dopant of a second conductivity type opposite to the first conductivity type into said substrate to produce first dopant implanted portions around a first projected range;
introducing, using said resist as a mask, a second

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