Semiconductor integrated circuit and semiconductor...

Details Semiconductor integrated circuit and semiconductor... Semiconductor integrated circuit and semiconductor...

2001-06-25

2003-05-27

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06571379

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and semiconductor integrated circuit wiring layout method capable of reducing the parasitic capacitance between different wiring layers.
FIG. 4
shows a layout having undergone automatic wiring processing by a conventional method. In
FIG. 4
, lower grid lines
10
are center lines for first aluminum wiring lines laid out in the X direction at the same pitch in the Y direction. Grid lines
20
above the grid lines
10
are center lines for second aluminum wiring lines laid out in the X direction at the same pitch in the Y direction. Grid lines
30
above the grid lines
20
are center lines for third aluminum wiring lines laid out in the X direction at the same pitch in the Y direction.
Similarly, lower grid lines
11
are center lines for first aluminum wiring lines laid out in the Y direction at the same pitch in the X direction. Grid lines
21
above the grid lines
11
are center lines for second aluminum wiring lines laid out in the Y direction at the same pitch in the X direction. Grid lines
31
above the grid lines
21
are center lines for third aluminum wiring lines laid out in the Y direction at the same pitch in the X direction.
First aluminum power supply wiring lines
110
and
111
, and first aluminum signal wiring lines
120
,
121
,
122
, and
123
are laid out in the X direction by using the grid lines
10
as center lines. Upper second aluminum signal wiring lines
210
,
211
,
212
,
213
,
214
, and
215
are laid out in the Y direction by using the grid lines
21
as center lines. Similar to the first aluminum signal wiring lines, upper third aluminum signal wiring lines
310
,
311
,
312
, and
313
are laid out in the X direction by using the grid lines
30
as center lines.
In
FIG. 4
, the start point coordinates of grid lines are set to the same in all the layers, and the wiring pitch is also the same. Thus, the first aluminum signal wiring line
120
and third aluminum signal wiring line
310
, the first aluminum signal wiring line
121
and third aluminum signal wiring line
312
, and the first aluminum signal wiring lines
122
and
123
and third aluminum signal wiring line
313
completely overlap each other.
As described above, the automatic layout technique of a semiconductor integrated circuit inevitably suffers a decrease in distance between adjacent wiring lines and overlap on an upper wiring line. A parasitic capacitance generated between wiring lines causes crosstalk.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor integrated circuit and semiconductor integrated circuit wiring layout method capable of reducing the parasitic capacitance between different wiring layers.
To achieve the above objects, according to the present invention, there is provided a semiconductor integrated circuit comprising a first wiring layer formed in a first direction, a second wiring layer formed in a second direction perpendicular to the first direction, and a third wiring layer formed in the second direction to sandwich the first wiring layer between the third wiring layer and the second wiring layer, wherein the second and third wiring layers are shifted from each other by a predetermined distance in the first direction.


REFERENCES:
patent: 4777606 (1988-10-01), Fournier
patent: 4893170 (1990-01-01), Tokuda et al.
patent: 5483461 (1996-01-01), Lee et al.
patent: 1-283847 (1989-11-01), None

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