Universal resource access controller

Details Universal resource access controller Universal resource access controller

1999-11-12

2003-03-11

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S005000, C710S006000, C710S015000, C710S017000, C710S018000, C710S019000, C710S040000, C710S062000, C710S240000, C710S244000, C711S100000, C711S147000, C711S150000

Reexamination Certificate

active

06532505

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains generally to computing systems. More specifically, the present invention relates to a providing access to shared resources in a computing system such as multi-processor computer systems and the like. More particularly, techniques for prediction of the time between two consecutive memory accesses are described.
BACKGROUND OF THE INVENTION
In a basic computer system, a central processing unit, or CPU, operates in accordance with a pre-determined program or set of instructions stored within an associated memory. In addition to the stored instruction set or program under which the processor operates, memory space, either within the processor memory or in an associated additional memory, is provided to facilitate the central processor's manipulation of information during processing. The additional memory provides for the storage of information created by the processor as well as the storage of information on a temporary, or “scratchpad”, basis which the processor uses in order to carry out the program. In addition, the associated memory provides locations in which output information from the processor's operating set of instructions is placed in order to be available for the system's output device(s).
In systems in which many components (processors, hard drive, etc) must share a common bus in order to access memory there is a high probability of memory access conflicts. Especially in the case of multiprocessor computer systems, and the like, in which different processors are simultaneously in operation, access to memory or other shared resources becomes complex. Since it is likely that each of the processors or processor systems may require access to the same memory simultaneously, conflicts between processors will generally be unavoidable. Essentially, the operation of two or more processors or processor systems periodically results in overlap of the memory commands with respect to a common memory, or other shared resource, in the multi-processor computer system.
Conventional approaches to solving the problem of conflicting memory access requests to a shared memory include, in one case, complete redundancy of the memories used for each of the processors, and isolation of the processor systems. However, this approach to solving the problem of conflicting memory access requests often defeats the intended advantage of the multiple processor system. Such multiple processor systems are most efficient if operated in such a manner as to provide parallel computing operations upon the same data in which one processor supports the operation of the other. Conventionally, such processor systems may be either time shared in which the processors compete for access to a shared resource, such as memory, or the processor systems may be dual ported in which each processor has its own memory bus, for example, where one is queued while the other is given access.
Various approaches have been used to avoid the above described conflict problems. In one approach, the avoidance of conflicts is accomplished by sequentially operating the processors or by time sharing the processors. In this way, the processors simply “take turns” accessing the shared resource in order to avoid conflict. Such systems commonly include “passing the ring” or “token systems” in which the potentially conflicting processors are simply polled by the system in accordance with a pre-determined sequences similar to passing a ring about a group of users.
Unfortunately, use of sequential processor access methodologies imposes a significant limitation upon the operation of the overall computer system. This limitation arises from the fact that a substantial time is used by the system in polling the competing processors. In addition, in the case where only a single processor is operating and requires access to the shared memory, for example, a delay occurs whenever the processor accesses the shared resource following each memory cycle as the system steps through the access sequence.
Another conventional approach to conflict avoidance relies upon establishing priorities amongst the processors in the computer system. One such arrangement provides every processor assigned to it a priority of system importance. The memory controller simply provides access to the highest priority processor every time a conflict occur. For example, in a two processor system, a first and a second processor access a shared memory which is typically a dynamic RAM (DRAM) type memory device which requires periodic refreshing of the memory maintain stored data. Generally, the DRAM type memory is refreshed by a separate independent refresh system. In such a multi-processor system, both the processors and the refresh system compete for access to the common memory. A system memory controller will process memory access request conflicts, or commands, as determined by the various priorities assigned to the processors and the refresh system. While such systems resolve conflicts and are somewhat more efficient than pure sequential conflict avoidance systems, they still suffer from lack of flexibility.
Another approach to conflict resolution involves decision-making capabilities incorporated in the memory controller. Unfortunately, because the decision making portions of the memory controller are operated under the control and timing of a clock system, a problem arises in that substantial time is utilized in performing the actual decision making before the memory controller can grant access to the common memory.
Unfortunately, this problem of performing the actual decision making substantially erodes the capability of conventional memory controllers granting access to multi-bank type memory systems. In multi-bank type memory systems, the actual memory core is departmentalized into specific regions, or banks, in which data to be retrieved is stored. Although providing faster and more efficient memory access, the complexity required of conventional memory controllers in coping with a multi-bank memory device substantially slows the overall access time of the system as a whole.
In view of the foregoing, it should be apparent that a method of speeding up a memory access of a memory page included in a memory bank in a multi-bank type memory by a memory controller is desired.
SUMMARY OF THE INVENTION
According to the present invention, a universal resource access controller is provided for controlling access to an associated resource comprising, for example, synchronous link DRAM (SLDRAM). The present invention includes a universal resource access controller coupled to a requesting system and a resource, such that when the requesting system desires access to the resource, the requesting system generates a resource access request which is passed to the universal resource controller. The universal resource controller, in turn, uses a specific characteristic operating parameter of the requested resource as well as a current state of the requested resource to generate a corresponding sequenced universal access request command suitable for accessing the resource as required by the requesting system.
In another embodiment of the invention, an apparatus for controlling access to any of a plurality of accessible devices by any of a plurality of requesting systems is disclosed. The apparatus includes a universal controller unit and an address space controller unit coupled to the universal controller unit. The universal controller unit decodes an incoming system address and an incoming system command provided by the requesting system. The universal controller unit then generates an associated device address and a corresponding device command based upon device parameters stored in and provided by the address space controller arranged in such a manner that each of the plurality of devices is accorded its own address region within the address space controller.


REFERENCES:
patent: 4354225 (1982-10-01), Frieder et al.
patent: 4803623 (1989-02-01), Klashka et al.
patent: 4831523 (1989-05-01), Lewis et al.
patent: 5530845 (1996

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