Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-07
2003-03-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06532570
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to designing integrated circuits to increase reliability. More specifically, the present invention relates to designing integrated circuits to reduce failures due to electromigration.
2. Description of the Related Art
The reliability of recent very large scale integration (also referred to as “VLSI”) designs has been improved through better alloys, additional layers and increasing grain size. However, designers continue to have aggressively pursue increased product performance. Pursuing increased performance leads to higher clock speeds and power dissipation, which increase thermal density and thermal stress. High current densities and thermal stresses drive degradation mechanisms in the interconnect system of VLSI circuits. Specifically, high current densities lead to electromigration-caused failures.
Electromigration (also referred to as “EM”) is an atomic diffusion phenomenon and refers to the transport of ions or atoms due to the high current densities and/or strong electric fields. Electromigration is a temperature activated process. Therefore, temperature will influence the amount and speed of migration of ions and atoms.
FIG. 1A
illustrates the mechanics of electromigration. As shown in
FIG. 1A
, electric current leaves the metal strip at the anode and is conducted to the cathode. The electrical current causes metal particles to migrate from the cathode side of the strip to the anode side of the strip. By definition, the electrical current is in the opposite direction to the electron flow. Thus, metal particles deplete the cathode side of the metal strip and accumulate on the anode side. Depletion of the cathode side can cause voids which can cause an open circuit. Accumulation on the anode side can lead to a hillock which can cause a short circuit. Thus, both accumulation and depletion can cause failure of a microprocessor or other integrated circuit.
Referring briefly to
FIG. 2
, an equation is provided to calculate the outgoing atomic flux per unit volume, referred to as the volumetric generation rate (∇·{right arrow over (J)}
A
). As illustrated in
FIG. 2
, the equation can be used to calculate the volumetric generation rate due to a structural inhomogeneity, a temperature inhomogeneity, a current density inhomogeneity or a material inhomogeneity. For example, current density inhomogeneity can be caused by two imposed currents on a single metal lead with a single anode and a single cathode. Flux divergence is the difference between flux received and flux transmitted. In structural inhomogeneity, flux is not transmitted evenly due to voids or other structural imperfections in the metal lead. The depletion and accumulation regions are not bound to the cathode or anode. These processes take place wherever an inhomogeneity causes a volumetric generation rate greater than zero.
FIG. 2
also depicts temperature inhomogeneity. The temperature inhomogeneity leads to an inhomogeneous atomic flux distribution which causes areas of depletion and accumulation of atoms. Finally,
FIG. 2
also represents the inhomogeneity due to mature constants. An inhomogeneity in the flux can be caused by an inhomogeneity of material constants. For example, inhomogeneity due to constants such as conductivity and diffusivity. These constants can be due to barrier layers between metals such as aluminum and copper in the metal lead.
As previously discussed (refer to FIG.
1
A), the transport of ions or atoms causes degradation and failure of metal connections in an integrated circuit. Thus, EM has remained a key variable in the design of integrated circuits. Designers compare interconnect direct charge average current per unit width, J′
eff
, to a fixed limit. For example:
S
=
Actual
J
eff
′
Design
Limit
J
eff
′
where:
S represents current density ratio
J′
eff
represents electrical current density per unit width in amps per centimeter
With appropriate modifications for contacts and alternating current lines the equation given above can be used to provide a conservative fixed limit. Previously, designers considered a design with S<1 a reliable design. Typically, designs producing S>1 have been subject to redesign.
However, from a reliability perspective, EM is inherently statistical. Failure times can vary widely for identically sized and stressed interconnects. An approach that factors EM failure statistics into the setting of EM design limits does not quantify chip reliability and does not reveal the relationship between S and EM risk. When reliable design is defined to mean achieving a chip-level reliability goal, fixed current density design limits become mathematically arbitrary. A design which has all interconnects to satisfy S<1 does not guarantee a reliable design. Similarly, a design including an interconnect with S>1 does not necessarily lead to an unreliable product. The total statistical risk is the critical variable in the design. Therefore, if each segment of interconnect at each stress level can be evaluated, the reliability goal can be distributed between interconnections. Distributing the reliability goal among classes of interconnections minimizes the performance limitation that an EM reliability goal places on the design.
Table 1 (below) demonstrates a typical non-linear relationship between maximum allowed current density and the number of violation corrections needed to reduce the current density below the allowable limit for a specific design.
TABLE 1
Current Density Limit
Number of
[amps/sq. cm]
Violations
3.17E6
9
2.58E6
17
2.10E6
52
1.71E6
97
1.39E6
162
1.13E6
337
0.93E6
616
Table 1 demonstrates that nine leads in the integrated circuit block must be redesigned (by widening the lead or other modification) to satisfy the current density limit of 3.17×10
6
amps per square centimeter. Similarly, for a current density of 2.58×10
6
amps per square centimeter, seventeen leads in the hypothetical integrated circuit block must be redesigned. Thus raising the allowable current density limit from 2.58×10
6
amps per square centimeter to 3.17×10
6
amps per square centimeter decreases from seventeen to nine the number of violations which must be addressed.
Still referring to Table 1, for a current density of 0.93×10
6
amps/cm
2
, 616 violations must be corrected before the current density design limit is satisfied. Thus, increasing the allowable current density design limit from 0.93×10
6
to 3.17×10
6
amps/cm
2
decreases the number of violations which must be satisfied from 616 violations to nine violations. Thus, the case illustrated by Table 1 shows that for an increase in the current density limit of approximately four times the number of violations that must be corrected is reduced by over 98%, a non-linear relationship. A preliminary VLSI design can have 2.1 million violations or more. Thus, increasing the allowable current density limit can have a significant impact on the number of potential violations to be addressed in a redesign.
FIG. 1B
is a graph of the number of interconnects versus the current density distribution. As shown in
FIG. 1B
(and as previously noted in Table 1), the relationship between the number of interconnects and the current density distribution is non-linear. Thus, an increase in the allowable current density can be expected to disproportionately lower the number of violations.
The relation between the divergence of atomic flux and the time to failure can also be modeled mathematically.
FIG. 3
shows the probability distribution function of the time to failure as a lognormal distribution. Thus,
FIG. 3
shows the probability of failure at a given time. The area under the curve is normalized to one so that the percentage of failed devices can be calculated by integrating the area under the curve from time to failure equal zero (TTF=0) to the time of interest.
The percent
Dinh Paul
Hamilton & Terrile LLP
Smith Matthew
Sun Microsystems Inc.
Terrile Stephen A.
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