Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-05-10
2003-04-01
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S105000, C365S222000
Reexamination Certificate
active
06542958
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to dynamic random access memories (DRAMs) and more particularly to reducing power consumption when utilizing such a memory.
BACKGROUND OF THE INVENTION
In computer systems where memory is shared among different programs, the OS (operating system) software decides which program gets to use which memory locations, generally consisting of eight bits (or a byte). The OS maintains a list of available memory locations, from which it selects the requested amount of memory locations to assign to the program making the request. The newly assigned memory locations are removed from the list of available memory locations. When a program is completed, the OS adds the memory locations that were used by the program to the list of available memory locations. If a system doesn't use an OS, then the application program or programs must collectively and cooperatively manage the sharing of the memory system.
In computer systems that provide an operating system, the application programs (all programs other than the OS) do not know of the physical locations of the memory that are assigned to them. This is achieved through a mechanism known as virtual memory system. The application programs specify a memory address known as virtual address, and the OS and the underlying hardware translates the virtual address to the corresponding physical address. In such systems, the application programs have no control over the physical memory system—only the OS has any and all control over the physical memory system.
To reduce the overhead of managing the memory system, a block of consecutive memory locations (or addresses) is treated as one unit, known as a page. The OS assigns one or more pages of memory locations to an application program. The size of a page can vary from system to system. One system may even support multiple page sizes. A common page size is 4K (4096) bytes.
Existing DRAM designs utilized in such computer systems require periodic refresh of all storage cells to prevent loss of data. Periodic refresh is needed even when DRAM is not being accessed for an extended period or when the data stored in DRAM is not valid.
In general, data in a memory location is deemed invalid until a program, which has exclusive access to the memory location for a period of time, has first written a known value to it. When a memory location is used by a program and is then released after the program is finished, the memory location is deemed to contain invalid information until it is re-assigned and is written a known value by another program. During this period, in which the memory location contains invalid data, existing DRAM chips refresh the memory location since they do not know that the memory location contains invalid data. Existing DRAM chips operate as if all cells in them always contain valid data. Accordingly, these cells are refreshed unnecessarily, thereby increasing power consumption of the overall system.
What is desirable is a mechanism for providing a DRAM refresh in a computer system only when needed rather than on regular basis. The system should be easy to implement, cost effective and adaptable to existing systems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for controlling refresh of a plurality of dynamic random access memory (DRAM) cells in a data processing system is disclosed. The method and system comprises of providing at least one valid bit to control the refresh of at least one row of DRAM cells and providing a set of commands by a software program to control the at least one valid bit.
Accordingly, a system and method in accordance with the present invention allows for software control of a DRAM refresh to reduce power consumption in a data processing system. In a system and method in accordance with the present invention, a plurality of valid bits are provided, each valid bit allows for a group of DRAM cells to suppress the refresh operation when a refresh is not needed. Each of the valid bits controls the refresh of all cells in a row of DRAM cells and all cells of a memory location are contained in one row. A system and method in accordance with the present invention utilizes a set of commands to set or clear a valid bit, which allows the software to control the refresh. The plurality of valid bits are preferably implemented using the DRAM cells but without providing a refresh mechanism.
REFERENCES:
patent: 5396635 (1995-03-01), Fung
patent: 5758175 (1998-05-01), Fung
patent: 5764582 (1998-06-01), Tai
patent: 5781782 (1998-07-01), Tachikawa
patent: 5828619 (1998-10-01), Hirano et al.
patent: 5877651 (1999-03-01), Furutani
patent: 5928365 (1999-07-01), Yoshida
patent: 5966725 (1999-10-01), Tabo
patent: 6021502 (2000-02-01), Ando
patent: 6079025 (2000-06-01), Fung
patent: 6115823 (2000-09-01), Velasco et al.
patent: 6167484 (2000-12-01), Boyer et al.
Elan Research
Sawyer Law Group LLP
Thai Tuan V.
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