Multi-port static random access memory equipped with a write...

Details Multi-port static random access memory equipped with a write... Multi-port static random access memory equipped with a write...

2001-07-10

2003-03-25

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S156000, C365S190000, C365S227000, C365S226000

Reexamination Certificate

active

06538954

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi port SRAM (Static Random Access Memory) including MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and, more particularly, to a technique for reading and writing data from and into memory cells of the SRAM.
2. Description of the Background Art
In an integrated circuit, an SRAM is used to cache data or instructions, i.e., to function to temporarily hold data therein for transmission of data to a CPU (Central Processing Unit) in timed relation to the CPU and to store the state of a sequential circuit therein. In recent years, emphasis has been placed on the rate at which data is written into and read from the memory. To increase a memory bandwidth, there has been proposed a technique in which a plurality of I/O ports are provided to the memory cells of the SRAM. Examples of this technique include a dual port static memory cell having one read port and one write port, and a multi port static memory cell having a multiplicity of read ports and a multiplicity of write ports.
FIG. 51
conceptually illustrates a configuration of a background art SRAM including a memory cell array and its peripheral components. Memory cells in the array are disposed in a matrix having m rows and n columns, and a memory cell in the i-th row, j-th column is designated by MC
ij
. In
FIG. 51
is shown the reference character MC
13
designating a memory cell disposed in the first row, the third column.
The SRAM shown in
FIG. 51
is configured to have word lines extending along the rows and bit lines extending along the columns. A word line decoder
3
is connected to word line groups
30
i
(i=1, 2, 3, . . . , m−1, m), and selectively activates a word line group
30
i
corresponding to a row address RA inputted thereto. A bit line decoder
4
is connected to bit line groups
40
j
(j=1, 2, 3, . . . , n−1, n), and selectively activates a bit line group
40
j
corresponding to a column address CA inputted thereto.
The word line groups
30
i
and the bit line groups
40
j
intersect each other at the memory cells MC
ij
. In other words, a common word line group is provided in corresponding relation to a plurality of memory cells arranged along each row, and a common bit line group is provided in corresponding relation to a plurality of memory cells arranged along each column.
Each of the word line groups
30
i
includes a write word line
31
i
, a read word line
33
i
, and a read complement word line
32
i
. The read word line
33
i
and the read complement word line
32
i
constitute a read word line pair. Each of the bit line groups
40
j
includes a write data bit line
41
j
, a write data complement bit line
42
j
, and a read data bit line
43
j
. The write data bit line
41
j
and the write data complement bit line
42
j
constitute a write data bit line pair.
FIG. 52
is a circuit diagram illustrating a common structure of every memory cell MC. Since the structure of the memory cells MC is not dependent basically upon the row and column locations (i, j), the subscripts denoting the row and column locations are omitted in FIG.
52
.
The memory cell MC shown in
FIG. 52
comprises a storage part (referred to hereinafter as a “storage cell”) SC having a pair of inverters L
1
and L
2
comprising a cross-coupled latch circuit, a read circuit RK, and access transistors QN
3
and QN
4
.
In the storage cell SC, the inverter L
1
has transistors QP
1
and QN
1
connected in series, and the inverter L
2
has transistors QP
2
and QN
2
connected in series. The read circuit RK comprises a tristate inverter having transistors QP
3
, QP
4
, QN
5
, QN
6
connected in series.
N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the transistors QN
1
to QN
6
, and P-type MOSFETs are used as the transistors QP
1
to QP
4
. For example, the N-type MOSFETs are of a surface-channel type, and the P-type MOSFETs are of a surface-channel or buried-channel type.
The storage cell SC further comprises a pair of nodes N
1
and N
2
which have a pair of storage states: the nodes N
1
and N
2
are “high” and “low” respectively, and vice versa. A “high” means a logic corresponding to a potential higher than (V
DD
+V
SS
)/2, and a “low” means a logic corresponding to a potential lower than (V
DD
+V
SS
)/2 where a ground is often selected as the potential V
SS
. A “high” and a “low” mean not only the logics but also potentials corresponding to the respective logics. Which of the “high” and “low” states represents a “1” as a bit of the SRAM and which represents a “0” is a matter of design choice.
The N-type MOSFET turns on when a “high” is applied to the gate thereof, and turns off when a “low” is applied thereto. The P-type MOSFET turns on when a “low” is applied to the gate thereof, and turns off when a “high” is applied thereto. In an “on” state, current flows between the source and the drain of the MOSFET to provide electrical conduction therebetween. In an “off” state, there is electrical disconnection between the source and the drain of the MOSFET and almost no current flows therebetween.
The node N
1
is the input of the inverter L
2
, and a potential corresponding to a logic complementary to the logic corresponding to the potential at the node N
1
is outputted to the node N
2
. The node N
2
is the input of the inverter L
1
, and the inverted bit of a logic complementary to the logic corresponding to the potential at the node N
2
is outputted to the node N
1
. Thus, there are a pair of storage states corresponding to complementary logics.
The access transistor QN
3
is connected at nodes N
1
and N
4
to the storage cell SC and the write data bit line
41
, respectively. The access transistor QN
4
is connected at nodes N
2
and N
5
to the storage cell SC and the write data complement bit line
42
, respectively. The gates of the respective access transistors QN
3
and QN
4
are connected commonly to the write word line
31
.
In the read circuit RK, the drains of the respective transistors QP
4
and QN
5
are connected commonly to a node N
3
. The gates of the respective transistors QP
3
and QN
6
are connected commonly to the node N
1
. The gates of the transistors QP
4
and QN
5
are connected to the read complement word line
32
and the read word line
33
, respectively. As described above, a dual port static memory cell is used as the memory cell MC.
For reading data from the memory cell MC, complementary logics are placed on the read word line
33
and the read complement word line
32
. The read word line
33
and the read complement word line
32
corresponding to a row including the memory cell MC to be read are driven high and low, respectively, whereas the read word lines
33
and the read complement word lines
32
corresponding to the other rows are driven low and high, respectively.
Thus, both of the transistors QP
4
and QN
5
of the read circuit RK in the memory cell MC to be read turn on. This causes an inverter comprised of the transistors QP
3
and QN
6
to apply a value complementary to the value at the node N
1
through the node N
3
to the read data bit line
43
. On the other hand, the transistors QP
4
and QN
5
of the read circuit RK in each of the memory cells MC which are not to be read turn off. This disconnects the read data bit line
43
from the storage cell SC in each of the memory cells MC which are not to be read.
For writing data into the memory cell MC, the write word line
31
corresponding to a row including the memory cell MC to be written is driven high, whereas the write word lines
31
corresponding to the other rows are driven low.
Thus, both of the access transistors QN
3
and QN
4
in the memory cell MC to be written turn on. This connects the nodes N
1
and N
2
of the storage cell SC through the nodes N
4
and N
5
to the write data bit line
41
and the write data complement bit line
42
, respectively. On the other hand, the access transistors QN
3
and QN
4
in each of the memory cells MC which are

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