Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-09-21
2003-05-13
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S527000, C438S163000, C438S181000
Reexamination Certificate
active
06562671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor display device having a circuit comprising thin film transistors (hereinafter referred to as TFTs) and a manufacturing method thereof. As the semiconductor display device, there is an electro-optical device such as a liquid crystal display and an EL (electroluminescence) display, which comprises, for example, the TFTs.
2. Description of the Related Art
Recently, an active matrix liquid crystal display technique using the TFT is noted. An active matrix display is superior to a passive matrix display in a response speed, a view angle, and a contrast. Thus, this currently becomes the mainstream of a note type personal computer, a liquid crystal television, or the like.
The TFT is generally constructed using amorphous silicon or polycrystalline silicon for a channel layer. In particular, a polycrystalline silicon TFT manufactured in a low temperature process (generally, 600° C. or lower) has the following characteristics. That is, a low cost and a large area can be achieved. Simultaneously, since an electron or a hole has a high electric field mobility, when such a TFT is used for the liquid crystal display, not only the integration of pixel transistors but also the integration of drivers as a peripheral circuit can be achieved. Thus, the development is progressed in each liquid crystal display maker.
However, when the polycrystalline silicon TFT is continuously driven, there is the case where a deterioration phenomenon such as a reduction in a mobility or an on-current (current flowing in the case where the TFT is in an on-state) and an increase in an off-current (current flowing in the case where the TFT is in an off-state) is observed. This is a large problem in reliability. This phenomenon is called a hot carrier phenomenon and it is known that this is due to a hot carrier produced by a high electric filed near a drain.
This hot carrier phenomenon is a phenomenon first discovered in a MOS transistor. Thus, as hot carrier measures, various basic studies have been made until now. In the case of the MOS transistor with a design rule of 1.5 &mgr;m or less, as measures to the hot carrier phenomenon by a high electric field near the drain, an LDD (Lightly Doped Drain) structure is employed. According to the LDD structure, low concentration impurity regions (n
−
regions) are provided in drain end portions by using side walls in the sides of a gate and an impurity concentration of the drain junction is made gradient to relax an electric field concentration near the drain.
In the case of the LDD structure, a drain withstanding voltage is greatly improved relative to a single drain structure. However, since the resistance of the low concentration impurity regions (n
−
regions) is large, there is such a defect that a drain current is decreased. Also, high electric field regions are present immediately under the side walls, impact ionization is maximized in those regions, and hot electrons are injected into the side walls. Thus, a deterioration mode inherent to the LDD, such as the low concentration impurity regions (n
−
regions) are depleted and resistance is increased becomes a problem. As a channel length is shortened, the above problems become apparent. Therefore, in the MOS transistor with 1.5 &mgr;m or less, as a structure for overcoming the problems, a GOLD (Gate-Overlapped LDD) structure in which the low concentration impurity regions (n
−
regions) are formed by overlapping the end portions of a gate electrode with each other is designed and employed.
Under such a background, even in the case of the polycrystalline silicon TFT as a constitution element of the liquid crystal display, as in the case of the MOS transistor, an application of the LDD structure and the GOLD structure is studied for the purpose of relaxing a high electric field near the drain. In the case of the LDD structure, the low concentration impurity regions (n
−
regions) and high concentration impurity regions (n+ regions) as a source region or a drain region outside the low concentration impurity regions are formed in a polycrystalline silicon layer corresponding to the outer regions of the gate electrode. Thus, although an effect for suppressing the off-current is large, there is such a defect that an effect for suppressing a hot carrier by relaxing the electric field near the drain is small. On the other hand, in the case of the GOLD structure, the low concentration impurity regions (n
−
regions) of the LDD structure is formed to overlap with the end portions of the gate electrode and a hot carrier suppressing effect is larger than in the LDD structure. However, there is such a defect that the off-current becomes large.
Also, as an example for studying the GOLD structure in an n-channel polycrystalline silicon TFT, for example, there is “Mutuko Hatano, Hajime Akimoto and Takesi Sakai, IEDM97, TECHNICAL DIGEST, pp.523-526, 1997”, in which a basic characteristic of the GOLD structural TFT is disclosed. In the basic structure of the GOLD structural TFT, the gate electrode and LDD side walls comprise polycrystalline silicon. Also, the low concentration impurity regions (n
−
regions) as electric field relaxation regions and the high concentration impurity regions (n
−
regions) as the source region or the drain region outside the low concentration impurity regions are formed in an active layer (comprising polycrystalline silicon) located immediately under the LDD side walls. With respect to the basic characteristic. compared with a general LDD structural TFT, a drain electric field is relaxed and a large drain current is obtained. Also, such a characteristic that an effect for suppressing a drain avalanche hot carrier is large is obtained.
A semiconductor display device such as the liquid crystal display device, which comprises the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit as a driver circuit and TFT characteristics required for each circuit are different. For example, an LDD structure polycrystalline silicon TFT having a large off-current suppressing effect is suitable for the pixel region. In addition, a GOLD structure polycrystalline silicon TFT having a large hot carrier resistance is suitable for the peripheral circuit as the driver circuit. When the performance of the semiconductor display device is improved, it is suitable that the pixel region comprises the LDD structure polycrystalline silicon TFTs and the peripheral circuit as the driver circuit comprises the GOLD structure polycrystalline silicon TFTs. However, since a manufacturing process is complicated, an increase in a manufacturing cost and a reduction in a yield become a large problem.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor display device capable of solving the above problems and a manufacturing method thereof.
According to the present invention, there is provided a semiconductor device comprising a plurality of thin film transistors formed on a transparent insulating substrate, each of said thin film transistors comprising: a semiconductor layer, a gate insulating film, and a gate electrode being laminated in order from a side near the transparent insulating substrate, and a source region and a drain region being formed in the semiconductor layer outside the gate electrode, wherein the gate electrode comprises a first layer gate electrode and a second layer gate electrode located on the first layer gate electrode and the first layer gate electrode is formed to have a longer size in a channel direction than the second layer gate electrode, wherein a first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode of the gate electrode, wherein a second impurity region and a third impurity region are formed adjacent to each other from a side near the gate electrode in the semiconductor layer corresponding to the outside of the gate
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Magee Thomas
Semiconductor Energy Laboratory Co,. Ltd.
Thomas Tom
LandOfFree
Semiconductor display device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor display device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor display device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3015503