Thin film transistor and fabricating method thereof

Details Thin film transistor and fabricating method thereof Thin film transistor and fabricating method thereof

2000-10-30

2003-07-22

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S154000, C438S526000

Reexamination Certificate

active

06596568

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 1999-47530, filed on Oct. 29, 1999, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to thin film transistors. More particularly, it relates to thin film transistors that are particularly useful as switching devices in liquid crystal displays, and to methods of fabricating such thin film transistors.
2. Discussion of the Related Art
Active layers of thin film transistors (hereinafter abbreviated TFTs) are formed on substrates. Such active layers include source and drain regions comprised of impurity doped materials and an undoped channel region. Impurity doping means that impurities are implanted into a substrate layer.
Impurities in source and drain regions tend to gather near the channel region when an ON signal is applied to a gate electrode located adjacent the active layer, thereby providing a path through which carriers can more easily pass.
To dope a semiconductor layer, doping impurities are accelerated using an acceleration voltage to kinetic energies in the range of 1 kV to 10 MV. The accelerated impurities are then directed onto a surface of a semiconductor. The accelerated impurities contact crystal lattices of the semiconductor and transfer their kinetic energy to those lattices. The doping impurities achieve an average penetration depth into the semiconductor that is referred to as the projected range (hereinafter abbreviated Rp).
While the projection range is a useful measure of the average penetration depth of the impurities, not every impurity locates at the projection range. Referring now to
FIG. 1
, doping impurities typically distribute with an impurity concentration profile that is almost symmetrically centering around the projected range Rp. The impurity concentration profile generally follows a Gaussian distribution having a maximum impurity concentration at Rp.
FIG. 1
also illustrates a measure of a distributional deviation called &Dgr;Rp.
FIG.
2
and
FIG. 3
present various illustrations of a related art TFT.
FIG. 2
illustrates a cross-sectional view of that related art TFT, while
FIG. 3
presents a graph of doping impurity concentration versus depth (into a semiconductor layer) of that related art TFT. Referring now to
FIG. 2
, a semiconductor layer
21
is formed on a buffer layer
20
that is over a substrate
200
. Over the center of the semiconductor layer is a gate insulating layer
22
that is covered by a gate electrode
23
. At one side of the semiconductor layer
21
is a source region
21
S that is doped with impurities, while the other side of the semiconductor layer has a drain region
21
D that is also doped with impurities. Below the gate insulating layer
22
is an undoped channel region
21
C.
To fabricate the related art TFT illustrated in
FIGS. 2 and 3
, impurity doping is carried out by accelerating doping impurities such that Rp is located less than 100 Å from the surface of the semiconductor layer
21
. Thus, the source and drain regions
21
S and
21
D are formed, as shown
FIG. 3
, by heavily doping the surface of the semiconductor layer
21
with impurities.
Unfortunately, TFTs according to
FIGS. 2 and 3
tend to have high leakage currents due to the high doping impurity concentrations at or near-the surface of the semiconductor layer when the TFT is in the OFF state. This leakage current is produced by current flow generated by carriers in the drain region when an electric field exists between the drain and gate electrode when the TFT is OFF. One approach to the problem of high leakage current is to incorporate an offset region between the gate and drain to reduce the electric field, the so-called lightly-doped-drain (LDD) structure. However, lightly-doped-drain TFTs usually require relatively complicated fabrication processes that include additional photo-masking and impurity doping steps to form the offset regions.
Moreover, TFTs according to
FIGS. 2 and 3
also have relatively high leakage current because of contaminants that cross the interface between the semiconductor layer and the buffer layer during the fabrication of the TFT.
Therefore, an improved thin film transistor, and a method of fabricating such a thin film transistor, having decreased leakage current would be beneficial.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to thin film transistors, and methods of fabricating such thin film transistors, that reduce the leakage current problems found in the related art.
An object of the present invention is to provide a thin film transistor, and a fabricating method thereof, having decreased leakage current achieved by reducing the electric field from the boundary of the drain region when an OFF voltage is applied, wherein the electric field is reduced by a doping step wherein impurities having a generally Gaussian distribution are formed such that the projection range Rp is located away from the surface of the semiconductor layer, and by having the impurities that remain at the surface of the semiconductor layer at a predetermined concentration which is relatively small.
Another object of the present invention is to provide a thin film transistor and a fabricating method thereof which has a small source/drain resistance produced by increasing the depth of Rp so as to reduce the surface impurities concentration, while maintaining the impurities above a predetermined level.
A further object of the present invention is to provide a thin film transistor and a fabricating method thereof which prevents contaminants from acting as a source of back channel current by compensating the amount of contaminants penetrating between a buffer layer and a semiconductor layer during the fabrication of a TFT by controlling the doping condition so as to have Rp located near or in the buffer layer.
Additional features and advantages of the present invention will be set forth in the description that follows, and in part will be apparent from that description and/or the drawings, or may be learned by practice of the invention. The objectives and other advantages of the present invention will be realized and attained by the structure discussed in the description and in the claims, as well as in the drawings.
To achieve these and other advantages of the present invention, as embodied and broadly described herein, there is provided a thin film transistor having a semiconductor layer having source and drain regions defined by doped impurities, a gate insulating layer and a gate electrode, wherein the impurities in the source and drain regions are implanted into the semiconductor layer such that the resulting impurity concentration profile has a projected range Rp at a depth that is away from the surface of the semiconductor layer, and wherein the impurities are distributed so as not to have a maximum concentration at the surface of the semiconductor layer.
In another aspect, the present invention relates to a method of fabricating a thin film transistor having a semiconductor layer with source, drain, and channel regions, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer. Those source and drain regions are defined by impurity doping the semiconductor layer, with the impurity doping carried out by setting doping impurity kinetic energies such that the doping impurities distribute into the semiconductor layer such that they do not have a maximum concentration at the surface of the semiconductor layer, and such that the impurities are implanted into the semiconductor layer so as to have a projected range Rp that is located at a depth that is away from the surface of the semiconductor layer.
In another aspect, the present invention relates to fabricating a thin film transistor having a buffer layer, a semiconductor layer on that buffer layer, a gate insulating layer over the semiconductor, and a gate electrode over the gate insulating layer. That semiconductor

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