Partitioned cache memory with switchable access paths

Details Partitioned cache memory with switchable access paths Partitioned cache memory with switchable access paths

1998-05-08

2003-03-18

Peikari, B. James (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S120000, C711S118000, C711S117000, C710S316000, C710S038000

Reexamination Certificate

active

06535960

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an information processing device equipped with a cache memory used by a central processing unit (CPU). Examples of such an information processing device are a microprocessor and a microcomputer.
2. Description of the Related Art
FIG. 1
is a block diagram of a first conventional information processing device, which is made up of a CPU
1
, an address bus
2
for transferring an address signal output by the CPU
1
, and a cache memory
3
used by the CPU
1
. The cache memory
3
is equipped with a hit/miss decision circuit
4
which determines whether an access to the cache memory
3
from the CPU
1
is a cache hit or a cache miss. An address bus
5
for transferring an address signal for an external address output from the cache memory
3
extends from the cache memory
3
. An external access request signal line
6
which transfers an external access request signal output from the cache memory
3
extends from the cache memory
3
.
Generally, a control register for an external resource, which may be a DMA (Direct Memory Access) controller, is designed so that the contents thereof can be changed without the CPU
1
. Hence, it is difficult to ensure coherency to the cache memory
3
. Hence, in an information processing device as described above, generally, an address area in which information that cannot be written into the cache memory
3
by an instruction access by the CPU
1
is stored is defined as a non-cachable area. For example, the control register for an external resource is defined as the non-cachable area.
The cache memory
3
is configured so as to refer to an address tag rather than determine whether an access from the CPU
1
is directed to the non-cachable area. Hence, when it is determined that the access is addressed to the non-cachable area, the access is determined as the cache miss in the cache memory
3
, and thereafter an external access is carried out.
FIG. 2
is a timing chart of an operation in the case where an access to the cache memory
3
by the CPU
1
is addressed to a non-cachable area in the cache memory
3
. Part (A) of
FIG. 2
shows clock signals &phgr;
1
and &phgr;
2
having respective phases and serving as operation clocks. Part (B) of
FIG. 2
shows a cache access address output to the cache memory
3
from the CPU
1
. Part (C) of
FIG. 2
shows an address tag look-up operation in the cache memory
3
in which a high level corresponds to the active state). Part (D) of
FIG. 2
shows an external access address output from the cache memory
3
, and part (E) thereof shows an external access request signal output from the cache memory
3
(a high level thereof is the active level).
When the CPU
1
accesses the cache memory
3
, the cache access address is output to the cache memory
3
from the CPU
1
. Upon receipt of the cache access address, the address tag regarding the cache access address is looked up in the cache memory
3
without determining whether the access from the CPU
1
is addressed to the non-cachable area. If the access from the CPU
1
is addressed to the non-cachable area, the hit/miss decision circuit
4
determines that the access is a cache miss. Then, the external access address for accessing an external memory is output from the cache memory
3
, and the external address request signal for requesting an access to the external memory is switched to the high level.
As described above, in the first device shown in
FIG. 1
, the access to the non-cachable area in the cache memory
3
from the CPU
1
is processed so that the hit/miss decision circuit
4
determines that the access is a cache miss and thereafter the external access is performed.
FIG. 3
is a block diagram of a second conventional information processing device, which includes a CPU
8
, an address bus
9
for transferring an address signal output by the CPU
8
, and a cache memory unit
10
used by the CPU
8
. The cache memory unit
10
is equipped with a hit/miss decision circuit which the access from the CPU
8
is a cache hit or a cache miss. The cache memory unit
10
is further equipped with a cachable area
on-cachable area decision circuit
12
. The circuit
12
has the function of determining in which one of address areas among address areas partitioned beforehand the address area of the access requested by the CPU
8
falls. Further, the circuit
12
has the function of determining whether the address area of the access requested by the CPU
8
is a cachable area by referring to a cachable area
on-cachable area indicating register (not shown) which has data indicating whether the address area of the access requested by the CPU
8
is a cachable area. The cache memory unit
10
has an OR circuit
13
, which performs an OR operation on the output signal of the hit/miss decision circuit
11
and the output signal of the decision circuit
12
.
The hit/miss decision circuit
11
switches its output signal to a low level when the access from the CPU
8
is a cache hit, and switches the output signal to the high level when the access is a cache miss. The decision circuit
12
switches its output signal to the low level when the access from the CPU
8
is addressed to the cachable area, and switches the output signal to the high level when the access is addressed to the non-cachable area. In short, the cache memory unit
10
determines whether the access from the CPU
8
is a cache hit and whether the above access is addressed to the cachable area.
An address bus
14
that transfers the address signal for an external address output from the cache memory unit
10
extends from the cache memory unit
10
. An external access request signal line
15
that transfers an external access request signal output from the cache memory unit
10
extends from the cache memory unit
10
.
FIG. 4
is a timing chart of an operation in a case where an access to the cache memory unit
10
by the CPU
8
is addressed to a non-cachable area in the second conventional device. Part (A) of
FIG. 4
shows clock signals &phgr;
1
and &phgr;
2
having respective phases and serving as operation clocks. Part (B) of
FIG. 4
shows a cache access address output to the cache memory
3
from the CPU
1
. Part (C) of
FIG. 4
shows an address tag look-up operation in the cache memory
3
in which a high level corresponds to the active state). Part (D) of
FIG. 4
shows an address area decision operation on the access requested by the CPU
8
, the operation being performed in the cache memory unit
10
(the high level of the signal shown in part (D) is the active state). Part (E) of
FIG. 4
shows a cachable area
on-cachable area indicating register loop-up operation in the cache memory unit
10
(the high level of the signal shown in part (E) is the active state). Part (F) of
FIG. 4
shows the external access address output from the cache memory unit
10
. Part (G) of
FIG. 4
shows the external access request signal output from the cache memory unit
10
(the high level is the active level).
When the CPU
8
accesses the cache memory unit
10
, the CPU
8
outputs the cache access address to the cache memory unit
10
. Upon receipt of the cache access address, the decision circuit
12
in the cache memory unit
10
makes a decision on the address area of the access requested by the CPU
8
. Subsequently, the cachable area
on-cachable area indicating register
12
is referred to, and the address area accessed by the CPU
8
is addressed to the cachable area. Further, in the cache memory unit
10
, the address tag is looked up independently of the decision operation on the accessed address area and the register loop-up operation.
When the decision circuit
12
determines that the access from the CPU
8
is addressed to the non-cachable area, the output of the decision circuit
12
is switched to the high level before the hit/miss decision circuit
11
switches its output signal to the high level. As a result, the external access address for an external access is output from the cache me

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