Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-31
2003-09-30
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S351000, C257S354000, C257S536000
Reexamination Certificate
active
06627952
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductors, and more particularly to methods and structures for rendering SOI-type semiconductors in various configurations.
BACKGROUND OF THE INVENTION
Existing complementary metal oxide silicon (CMOS) semiconductor devices that are produced in mass quantities are referred to as “bulk” CMOS, because they include a semiconductive bulk substrate on which active or passive circuit elements are disposed. Recently, silicon oxide insulator (SOI) devices have been introduced which consume less power than do bulk CMOS devices, an important advantage in many applications such as battery-powered mobile telephones and battery-powered laptop computers. Also, SOI devices advantageously operate at higher speeds than do bulk CMOS devices.
SOI devices are characterized by a thin layer of insulative material (the so-called buried oxide layer, or “SOI”) that is sandwiched between a bulk substrate and the circuit elements of the device. Typically, no other layers of material are interposed between the SOI and the bulk substrate. As used herein, the circuit elements establish a circuit component, such as an active transistor or passive component, e.g., a resistor.
In an SOI device, the circuit elements above the SOI are established by regions of field oxide and regions of a monocrystalline semiconductive layer which are doped as appropriate with N-type or P-type conductivity dopants. For example, for an N channel transistor, the isolated silicon layer will include a body region having a P-type dopant, with the body region being disposed between a source region and a drain region, each of which are doped with an N-type dopant, this forming an N channel metal oxide silicon field effect transistor (MOSFET) or a lateral NPN bipolar transistor, for example.
One disadvantage with SOI devices is that the voltage in body region tends to vary, or “float”. As noted by Chen et al. in “Suppression of the SOI Floating-body Effects by Linked-body Device Structure”, 1996 Symposium on VLSI Technology Digest of Technical Papers (1996 IEEE), consequences of floating body SOI devices include output current kinks, anomalous subthreshold currents, transient current overshoot, and early device breakdown.
Chen et al. propose suppressing the floating body effect by incompletely oxidizing the portion of a silicon layer that field oxidation is grown upon to allow field effect transistor (FET) bodies to be linked together through the unoxidized silicon layer remaining beneath the field oxide. However, Chen et al. do not suggest how to implement their floating body suppression strategy in various component configurations, nor do Chen et al. suggest how to implement their floating body suppression strategy using techniques that can be easily undertaken using existing bulk CMOS fabrication principles. As recognized herein, it is important to enable circuit designers to implement various SOI components using existing bulk CMOS fabrication principles, to promote the use of SOI devices without requiring the reengineering of semiconductor fabrication apparatus and facilities.
Moreover, Chen et al. do not recognize that in some potential SOI circuit component configurations, such as dynamic threshold metal oxide silicon (DTMOS) devices that operate at very low voltages, the floating body effect might be desirable to retain. Indeed, in some circuit element assemblies it might be desirable that some SOI components exhibit floating body characteristics, with the floating body tendency of other SOI components in the assembly being suppressed.
Accordingly, it is an object of the present invention to provide an SOI device in which floating body effects are minimized. Another object of the present invention is to provide an SOI device in which floating body effects can be selectively minimized in some regions of the device and not in others. Still another object of the present invention is to provide a variety of SOI devices in which floating body effects can be minimized using fabrication principles. Yet another object of the present invention is to provide an SOI device that is easy to use and cost-effective to manufacture.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device includes at least a first silicon oxide insulator (SOI) transistor and a second SOI transistor, and at least the first SOI transistor has a semiconductive body region. A semiconductive transition region is disposed between the first and second SOI transistors. The transition region has a first conductivity type and communicates with a power supply voltage source. In accordance with the present invention, the first conductivity type and the voltage source are selected to either isolate the first SOI transistor from the second transistor such that the body region of the first SOI transistor exhibits a floating effect, or to link the body region such that the body region does not exhibit a floating effect.
In the preferred embodiment, an ohmic connector connects the transition region to the voltage source. The transition region includes a relatively highly doped region and a relatively lightly doped region, and the ohmic connector contacts the relatively highly doped region. Per the present invention, the first transistor includes source and drain regions having the first conductivity type, and the transition region isolates the first SOI transistor from the second SOI transistor. In such an embodiment, the body of the first SOI transistor exhibits a floating effect. In contrast, when the first transistor includes source and drain regions having a second conductivity type opposite the first conductivity type, the transition region links the body region of the first SOI transistor with the voltage source such that the body of the first SOI transistor substantially does not exhibit a floating effect. When the source and drain regions are doped with an N-type dopant, the voltage source preferably is a transistor drain voltage source, and when the source and drain regions are doped with a P-type dopant, the voltage source preferably is a transistor source voltage source. Or, the power supply voltage source can output a variable voltage for establishing a biased metal oxide silicon (MOS) device.
Additionally, the first SOI transistor includes a gate, and the device can further includes a conductor interconnecting the gate and the transition region to establish a dynamic threshold metal oxide silicon (DTMOS) device. Alternatively, the first SOI transistor can include an emitter and a gate, and a conductor can interconnect the gate and the emitter to establish a lateral bipolar transistor. In such an embodiment, the gate has the first conductivity type.
In another aspect, a semiconductor SOI pinch resistor includes a silicon substrate and a silicon oxide insulator (SOI) layer on the substrate. At least one relatively lightly doped semiconductive region that has a first conductivity type is on the SOI layer. Also, at least first and second relatively highly doped semiconductive regions having the first conductivity type are disposed on the relatively lightly doped semiconductive region. Additionally, at least one field oxide layer is disposed between the first and second relatively highly doped semiconductive regions, and at least first and second ohmic connectors are respectively in contact with the first and second relatively highly doped semiconductive regions.
In still another aspect, a semiconductor SOI diode includes a silicon substrate and a silicon oxide insulator (SOI) layer on the substrate. At least one relatively lightly doped semiconductive region having a first conductivity type is disposed on the SOI layer, and at least first and second relatively highly doped semiconductive regions having respective first and second conductivity types are disposed on the relatively lightly doped semiconductive region. The first and second conductivity types are opposite of each other. At least first and second ohmic connectors are respectively in contact with the first and second relatively highly doped semicon
Advanced Micro Devices , Inc.
Fenty Jesse A.
Jackson Jerome
LaRiviere Grubman & Payne, LLP
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