Asynchronous latch design for field programmable gate arrays

Details Asynchronous latch design for field programmable gate arrays Asynchronous latch design for field programmable gate arrays

2001-07-17

2003-04-29

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S039000, C326S041000, C327S216000, C327S217000, C327S218000

Reexamination Certificate

active

06556043

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to logic device that uses a transparent latch technique to avoid glitches normally associated with RAM look-up tables. Particular utility of the present invention is found in field programmable gate arrays (FPGA), but has general applicability to any logic device.
2. Description of Related Art
FIG. 3
depicts a conventional field programmable gate array (FPGA)
10
. A typical FPGA comprises an array of programmable latch elements
12
and an array of programmable flip-flop logic elements
14
. A plurality of flip flop elements are programmed to operate as RAM devices formed into a look up table (LUT)
16
to generate a specified output given two or more input logic signals. Each look-up table receives two or more input signals, designated as signal
1
and signal
2
, and generates an output signal, for example, output
1
, output
2
, output
3
, . . . output n. When designing with FPGAs, general logic is normally implemented using RAM look-up tables. The look-up table operates on the defined input signal (signal
1
, signal
2
, etc.) and the RAM addresses or looks up the pre-programmed answer. While this technique is very efficient, by its very nature can produce glitches in certain situations. While look-up tables are very efficient and generally behave well in synchronous designs, glitches can be present at the outputs in asynchronous designs, i.e., where signal
1
and signal
2
are changing asynchronously.
One technique to remove the problems associated with look-up table designs in FPGAs has been the use of wired-and and wired-or structure based on tri-state internal buses with pull-up resistors. This approach is essentially an open collector technique and is hampered from a performance point of view since performance is limited by the inherently slow rise time (i.e., rc time constant) of the internal buses.
Accordingly, there exists a need to solve the glitch problem associated with asynchronous logic functions in field programmable gate arrays. There further exists a need to solve the aforementioned glitch problems associated with asynchronous logic design without requiring additional external logic to accomplish same.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a field-programmable gate array (FPGA), comprising an array of programmable latch elements, at least a portion of the latch elements have a data input, a clock input and a preset input; and an array of programmable flip-flop elements generating at least a first and second flip-flop output signals. At least one of said latch elements is adapted to form a preset dominant transparent latch where the first flip-flop output signal is coupled to the data input, the second flip-flop output signal is coupled to the preset input, and the clock input is held constant.
In broader aspects, the present invention provides programmable logic circuit, comprising an array of programmable latch elements, at least one of said latch elements having a data input and a preset input and adapted to form a preset dominant transparent latch; and a first data signal coupled to the data input and a second data signal coupled to the preset input, each data signal representing logic input data.
In the programmable logic circuit and/or FPGA, the preset dominant transparent latch is used in place of a conventional look-up table to generate said desired output signal. Also, the preset dominant transparent latch operates as a primitive logic device wherein the preset dominant transparent latch generates an output signal having a value of the first data signal (e.g., the first flip-flop output signal) OR the second data signal (e.g., the second flip-flop output signal). Alternatively, the preset dominant transparent latch generates an output signal having a value of the first data signal NOR the second data signal.
In method form, the present invention provides a method of replacing a look-up table in an FPGA, said method comprising the steps of designating a conventional latch element as a preset dominant transparent latch (PDTL); supplying a first data signal to a data input of said PDTL; and supplying a second data signal to a preset input of said PDTL. The method can further include the step of supplying a constant signal to a clock input of said PDTL.


REFERENCES:
patent: 5319254 (1994-06-01), Goetting
patent: 5646547 (1997-07-01), Goetting
patent: 5649167 (1997-07-01), Chen et al.
patent: 5821773 (1998-10-01), Norman et al.
patent: 5844844 (1998-12-01), Bauer et al.
patent: 6011730 (2000-01-01), Sample et al.
patent: 6211696 (2001-04-01), Skahill et al.

Affiliated with

Also associated with

Rating

Asynchronous latch design for field programmable gate arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Asynchronous latch design for field programmable gate arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous latch design for field programmable gate arrays will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3011940