Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-01-16
2003-03-18
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S595000, C438S651000, C438S652000, C438S660000, C438S663000, C438S682000, C438S692000
Reexamination Certificate
active
06534390
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to semiconductor devices and to an improved method of making a semiconductor device. More particularly, the present invention relates to a method to form silicide utilizing a silicon/ amorphous silicon/metal (SASM) structure, and laser annealing.
2. Description of Prior Art
Semiconductor devices are well known in the art. Conventional semiconductor structure often includes self-aligned suicides that are formed by Rapid Thermal Annealing (RTA) process. However, this process may result in suicides with poor uniformity, and has a tendency to consume source/drain junctions during silicidation as junction depths continue to decrease to less than 100 nm. In addition the process always has a silicide etch-back step after the first silicidation step to prevent bridging of the gate to the source/drain regions, which the current invention avoids.
For Example, U.S. Pat. No. 6,060,392 (Essaian et al.) discloses a laser anneal silicide process, however this process does not teach a key last CMP step of the current invention. U.S. Pat. No. 5,940,693 (Maekawa), U.S. Pat. No. 5,988,272 (Ishida et al.), and U.S. Pat. No. 6,074,900 (Yamazaki et al.), all show other laser anneal silicide processes.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an improved semiconductor device and method of making an improved semiconductor device using a SASM structure. Another purpose of the present invention is to use laser annealing for the formation of thick (low sheet resistance) silicide film on shallow source/drain regions. The extremely high ramp-up rate which is near zero thermal budget of the laser anneal allows melting and intermixing of the metal and silicon atoms. A Chemical Mechanical Polishing (CMP) step is used to break the continuity of the silicide film extending from the gate to Source/Drain regions instead of a silicide etch-back step.
The method of this invention includes the formation of a semiconductor device having a substrate and forming a gate dielectric layer over the substrate. A gate layer is formed over the gate dielectric layer, and then a cap layer is formed over that. After creating a lightly doped source/drain extension region in the substrate, spacers are formed on the side of the gate dielectric layer, gate layer, and cap layer, resulting in an intermediate structure. A deep source/drain region is then formed in the substrate. This is followed by an annealing step to activate dopants. The cap layer is then removed, and silicon film is deposited over the whole structure so far. A metal layer is then deposited over the silicon film. Using laser irradiation on the silicon film and the metal then creates a silicide. A pre-metal dielectric layer is then deposited and a chemical mechanical polishing is used to break the continuity of the silicide.
Semiconductor devices are well known in the art, and it is well known in the art that they can be either an N-MOS transistor or a P-MOS semiconductor.
The inventor has found the laser anneal process has advantages over conventional RTA and the advantages are: an extremely high heating and cooling rate; ability to form fine-grained suicides; and capability of heating only the top surface region. Another advantage, besides the laser process, is the SASM structure, which has the advantages of providing additional silicon for silicidation, thus forming thick silicide without junction consumption.
REFERENCES:
patent: 5940693 (1999-08-01), Maekawa
patent: 5998272 (1999-12-01), Ishida et al.
patent: 6060392 (2000-05-01), Essaian et al.
patent: 6074900 (2000-06-01), Yamazaki et al.
patent: 6316319 (2001-11-01), Ishida et al.
patent: 6376885 (2002-04-01), Tseng
patent: 2001/0038136 (2001-11-01), Abiko
Cha Randall
Chong Yung Fu
Pey Kin Leong
Chartered Semiconductor Manufacturing Ltd.
Chaudhuri Olik
Lee Hsien Ming
Pike Rosemary L. S.
Stoffel William J.
LandOfFree
Salicide method for producing a semiconductor device using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Salicide method for producing a semiconductor device using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Salicide method for producing a semiconductor device using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3011584