SRAM with write-back on read

Details SRAM with write-back on read SRAM with write-back on read

2001-06-08

2003-04-22

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S205000, C365S189011

Reexamination Certificate

active

06552923

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to data storage, and more specifically to RAM storage cells.
Many different types of data storage are used in various parts of a computer system. Non-volatile memory retains its data even when power is not applied. Volatile memory requires energy to retain its data. Two types of volatile memory are static and dynamic random-access memory (RAM).
RAM data storage is memory in which any cell can be randomly accessed for read and write by inputting the coordinates of that cell on the address pin. Basic RAM architecture can include inputs, outputs, addresses, read control, write control, and data storage. The basic cell stores two well defined states in a repeatedly accessible location.
Capacitors and latches are commonly used as RAM storage cells. These types of storage are susceptible to instability under certain circumstances, namely on read (when the stored data is accessed) and on standby (when the stored data is not being accessed).
Background: Standby Instability
Cells that use capacitors are normally unstable on standby, since charge stored in capacitors tends to leak away with time. The data stored in capacitors must therefore be periodically refreshed. Refreshing data consists sensing the state stored in the cell (1 or 0) and writing that state back to the cell, thus restoring the memory cell to its original state. Periodic refresh is a source of power consumption in standby. Storage cells that store charge on a capacitor and require refresh are termed dynamic RAM, or DRAM.
In addition to requiring periodic refresh, the sensing or reading of information in a DRAM cell upsets the storage state, destroying the stored information. The information must be restored to the cell (usually by writing the state back into the cell) within the read cycle.
Latches use bistable flipflops to store data. Typical storage cells are shown in
FIGS. 1
a
-
1
c
.
FIG. 1
a
shows a 6T SRAM cell with PMOS load devices. Data are stored as voltage levels with the two sides of the flipflop in opposite voltage states. The load devices offset charge leakage at the drains of the driver and access transistors.
FIG. 1
b
shows a similar cell that uses resistors rather than transistors. This permits reduction in cell size because the resistors can be stacked on top of the cell, but also has higher leakage in standby, trading performance for cost.
FIG. 1
c
shows a standard 4T SRAM storage cell. This cell uses two PMOS transistors as pass transistors and two NMOS transistors as drive transistors.
Data storage will be discussed with reference to
FIG. 1
c.
The storage states are determined by the relative potential between the two nodes, A and B. When node A is high, transistor
102
conducts, which grounds node B. Grounding node B turns off transistor
104
, which maintains the high potential at A.
Transistors experience leakage due to subthreshold currents even when the transistor is off. To maintain high node voltage, the on p-channel transistor (6T cell), resistor (4T-2R cell), or subthreshold current of the pass transistor (4T cell) must be enough to counter the subthreshold current of the off n-channel drive transistor plus any other leakage current at that node. For the 4T cell, it may be necessary to lower the wordline voltage. This will maintain the stored high voltage state by increasing the p-channel pass gate transistor subthreshold current. It is desirable to minimize the current required to maintain the stored voltage state. For DRAM, where the stored voltage is maintained by charge stored on a capacitor, the leakage or subthreshold currents limit the time for which the stored voltage can be maintained. The DRAM cell must therefore be periodically refreshed through a read and write-back to the cell.
Background: Read Instability
A bit stored in a memory cell is accessed by its row and column address.
FIG. 2
shows a RAM storage architecture. The row decoder
202
selects a row address from the N rows. All M cells on that row, or wordline, are activated. The column decoder
204
then selects a subset of the M bits for output. There may be one sense amp per column, and the column select chooses from the output of the M sense amps. Alternatively, there may be fewer sense amps than columns, and the column decode selects which columns are to be connected to the sense amps. If there is more than one sense amp, the column select may further select among the outputs of the multiple sense amps. In
FIG. 2
, the sense amplifier
208
detects the voltage differential between the two bitlines of the selected column, amplifies this voltage difference, and sends the data out of the array. A read-write control circuit
206
controls Input and Output.
In a cell with PMOS pass transistors, the wordlines are maintained high to keep the cell isolated from the bitline. Keeping the wordline high keeps the PMOS transistor from conducting. When a wordline is accessed, its voltage is lowered, which turns on the pass transistors. This connects all cells in that wordline to the associated bitlines. PMOS pass transistors
106
,
108
are shown in
FIG. 1
c.
The state of every cell on that wordline is potentially disturbed at this point because of the precharge on the bitlines. Referring back to
FIG. 1
c,
assume that node B is in a low potential state, and node A is high. If the bitlines are precharged high, the low side of the storage cell must pull that bitline low to establish a differential voltage on the bitlines for detection. At the same time, the charge on the bitline will tend to pull node B high.
In a perfectly balanced case, a differential voltage between node A and node B will be maintained and the memory state will be retained. However, if there are asymmetries in the cell that prefer the state where node A is low, the memory cell may be upset when accessed. The amount of asymmetry that can be tolerated without upset of the memory cell when accessed is referred to as the noise margin. The magnitude of the noise margin is affected by the strength (drive current capacity) of the drive transistor relative to the strength of the pass transistor in the memory cell. The stronger the drive transistor relative to the pass transistor, the greater the noise margin.
It should be noted that even if the memory is upset on access, there will be an initial differential voltage imposed on the bitlines reflecting the original state of the accessed memory cell. One design criterion for SRAM cells has been that they have sufficient noise margin to not upset on access for anticipated ranges of asymmetry at expected operating conditions. In contrast, memory is expected to be lost on access of DRAM cells. For DRAM cells the initial voltage imposed on the bitline is detected. The detected state of the accessed memory cell is subsequently written back into the accessed cell, restoring the original state.
Background: Cell Beta
Many important features in a memory cell depend at least in part on the dimensions of the transistors. A transistor is formed on a chip wherever a polysilicon path crosses a diffusion path, as shown in FIG.
3
. The leakage or off-state current of a transistor is proportional to W. The leakage current dependence on L is more complex, but generally leakage decreases with increases of L from the minimum design values. Thus the ratio of W to L determines both the drive and off-state capacity of the transistor. As this ratio increases (i.e., as W increases or as L decreases), the drive capacity increases. This ratio is referred to as W/L.
In SRAM storage cells, the operation and stability of the cell in standby and on read is influenced by these ratios. The ratio between the drive capacity of the drive transistors to the drive capacity of the pass transistors is called the cell beta. For the 4T cell, if cell beta is designed to be high (i.e., the drive transistors have greater drive and leakage current capacity than the pass transistors), then the cell will be unstable on standby, but stable on read. Conversely, if the 4T cell beta is d

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