Output buffer for digital signals

Details Output buffer for digital signals Output buffer for digital signals

2000-10-06

2003-04-08

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S029000, C326S083000, C327S170000, C327S558000

Reexamination Certificate

active

06545503

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an output buffer for digital signals, and more particularly to an output buffer providing a digital output with edges having shallower slopes than the edges of a digital input signal and the precise setting of the slopes.
BACKGROUND OF THE INVENTION
In some applications of output buffers for digital signals, for example, in data-transmission circuits and in multi-output digital circuits (such as RAMs, ROMs and EEPROMs with microprocessors), two problems in particular have to be addressed.
One of these problems, so-called “ground bouncing,” is due to the simultaneous switching of many output stages. In this situation, very high-pulsed currents pass through the parasitic resistances and inductances associated with the electrical connections between the integrated circuit and the external terminals, that is, the interconnection wires and the metal strips of the terminal conductors. These transient currents cause variations in the supply potentials (ground and VDD) which may give rise to spurious internal switching and hence to loss or alteration of the data associated with the digital signal. Another effect of the transient currents is the emission of intense, high-frequency electromagnetic radiation that may interfere with other circuits in the integrated device and that may also be propagated into the surrounding environment, contributing to the emission of potentially harmful radiation.
The other problem relates to the transmission of digital signals on lines outside the integrated circuit. If the line is not perfectly matched, which almost always occurs to a more or less marked extent with wide-band transmission, a very rapid transition between the two levels of the digital signal, that is, a stepped signal with a very steep front, causes a reflected wave. With a high degree of mismatch, the reflected wave may interfere with the signal to the extent of preventing its correct transmission.
A known output buffer that reduces the rate of transition of the output signal is illustrated in FIG.
1
. The buffer is constituted by three pairs of complementary MOS transistors (M
1
n
, M
1
p
; M
2
n
, M
2
p
; M
3
n
, M
3
p
), which are connected in a push-pull arrangement between two supply terminals, indicated by the ground symbol and +VDD, and which have their drain electrodes connected together to an output terminal
10
. The gate electrode of each transistor is connected to a separate terminal of a generator
11
for generating phase-shifted voltages. The input
12
of the generator is also the input of the buffer.
When, for example, the input signal Vin changes from a low logic state to a high logic state, three signals V
1
p
, V
2
p
, V
3
p
identical to the input signal Vin but delayed in sequence by a predetermined period of time, and three signals V
1
n
, V
2
n
, V
3
n
all at the reference (ground) potential, appear at the outputs of the generator. A potential is thus established at the gate electrodes of the p-channel transistors such as to make the transistors M
1
p
, M
2
p
, M
3
p
conductive one after another whilst the transistors M
1
n
, M
2
n
, M
3
n
remain non-conductive. An increasing current due to the successive conduction of the transistors M
1
p
, M
2
p
and M
3
p
will thus pass through the load (not shown) connected to the output of the buffer and a voltage step with an amplitude of approximately VDD, with a leading edge less steep than that of the input signal Vin will be formed at the output
10
. Similarly, a transition of the input signal Vin from a high logic state to a low logic state will bring about successive conduction of the transistors M
1
n
, M
2
n
and M
3
n
and hence the formation at the output
10
of a voltage step with an amplitude of approximately VDD, with a trailing edge less steep than that of the input signal Vin.
Although the known arrangement described above is sound in principle, in practice, it can be used only in non-critical applications because the slope of the edges of the output signal cannot be determined with sufficient accuracy at the design stage. This disadvantage is due both to the variability of the parameters of the production process, as a result of which the delay times of the signals to be applied in sequence to the gate electrodes of the transistors cannot be predetermined with certainty, and to the dependence of the parameters which cause the delays on environmental operating conditions (particularly temperature).
SUMMARY OF THE INVENTION
The disclosed embodiment of the present invention provides an output buffer that can provide a digital output signal with edges having shallower slopes than the edges of the digital input signal and in which the slopes can be set precisely.
The foregoing is achieved by the provision of an output buffer that has a slope-variation circuit generating an output signal having transition times longer than an input signal and a negative feedback circuit that generates a regulating signal to the input of the buffer that is dependent on the variation in the output signal.


REFERENCES:
patent: 5041741 (1991-08-01), Steele
patent: 5111076 (1992-05-01), Tarng
patent: 5489873 (1996-02-01), Kamata et al.
patent: 5543753 (1996-08-01), Williamson
patent: 5805020 (1998-09-01), Danz et al.
patent: 6198322 (2001-03-01), Yoshimura
patent: 0678983 (1995-10-01), None
patent: WO91/20129 (1991-12-01), None

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