Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-18
2003-03-18
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S398000, C438S255000
Reexamination Certificate
active
06534815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device with a stack electrode formed using HSG (hemi-spherical grain) growth and a method of manufacturing the same.
2. Description of the Related Art
A technique is known in which small unevenness is formed on the surface of a stack electrode using HSG growth to increase a surface area of the stack electrode, resulting in increase of a memory capacitance.
FIGS. 1A
to
1
C show a conventional method of forming the stack electrode for a memory capacitor using the HSG growth.
First, as shown in
FIG. 1A
, an oxide film
22
is formed on a silicon substrate
21
. A capacitance contact hole is formed to pass through the oxide film
22
to the silicon substrate
21
. An amorphous silicon (a-Si) layer containing the impurity ions such as phosphorus ions is grown at the temperature of 500 to 550° C. using a SiH
4
gas and a PH
3
gas to have the film thickness of 200 to 1000 nm. For example, the amorphous silicon layer is processed to form an amorphous silicon film
24
by use of a photolithography method and an etching method, to meet the shape of the stack electrode section. As a result, the stack electrode section composed of a stack section
20
and a capacitance contact section
23
is formed.
Next, as shown in
FIG. 1B
irradiation of SiH
4
and heat treatment are performed in vacuum at the temperature of 500 to 600° C., so that nuclei
27
for HSG grains
11
are formed only on the surface of a stack electrode. The crystallization progresses from the interface between the capacitance contact section
23
and the oxide film
22
toward the surface of the stack section
20
, at the same time as the formation of the HSG grains
11
progresses in the surface of the stack section
20
. This is because the growth temperature of the HSG grain
11
is near the crystallization temperature of the amorphous silicon. In this way, crystallization section
25
is formed.
Next, as shown in
FIG. 1C
, the HSG grains
11
are normally formed on most of the surface of the stack section
20
at this time. However, the crystallization from the interface between the contact section
23
and the oxide film
20
reaches the stack section surface partially, before all the HSG grains
11
are formed. Therefore, no HSG grains
11
are formed at the part
26
where the amorphous silicon is crystallized. The part
26
remains as an HSG grain formation defect section.
The stack electrode containing the HSG grain formation defect section has a smaller surface area, compared with the case where the HSG grains
11
are formed on the whole surface. The electrode surface area becomes small. For this reason, a charge quantity which can be stored in a capacitor decreases so that the charge holding time becomes short in case of a DRAM operation, resulting in a fault bit. Therefore, it is necessary to restrain the defect of the HSG grains due to the crystallization from the interface between the contact section
23
and the oxide film
22
.
The crystallization of the amorphous silicon film progresses faster as the phosphorus ion concentration is increased in the amorphous silicon film. Therefore, as one method to prevent the crystallization, it could be considered that the phosphorus ion concentration is decreased in the phosphorus doped amorphous silicon film
24
for the stack electrode. If this method is used, the generation of HSG grain formation defect section due to the crystallization can be effectively restrained. However, there is a problem in this method that the surface area increase through the formation of the HSG grains
11
does not contribute to the increase of the memory capacitance.
In order to sufficiently restrain the crystallization, the concentration of the phosphorus ions in the film must be made equal to or less than 1×10
20
cm
−3
. When an amorphous silicon with phosphorus ions doped in such low concentration is used, the phosphorus ion concentration in the HSG grain decreases. Therefore, when voltage is applied to the memory capacitor, a depletion layer is formed to extend from the HSG grain so that the memory capacitace value decreases, as shown in FIG.
3
.
Therefore, when a phosphorus doped amorphous silicon with the low concentration equal to or less than 1×10
20
cm
−3
is used, it is necessary that impurity ions are doped after the HSG grain formation to increase the phosphorus ion concentration in the HSG grain. Thus, the formation of the depletion layer because of HSG grains with low impurity ion concentration can be restrained. However, it is difficult to externally dope impurity ions into the inside of the stack electrode. In this case, because the phosphorus ion concentration in the amorphous silicon remains low, the contact resistance between the stack electrode and the substrate becomes high.
In conjunction with the above, in Japanese Laid Open Patent Application (JP-A-Heisei 6-204426) is described a method of forming a storage node electrode in a stacked type DRAM. In this reference, a contact hole is filled with a doped amorphous silicon and an undoped amorphous silicon is formed only on a stacked electrode. Therefore, a crystallization would progress in a heat treatment.
Also, in Japanese Laid Open Patent Application (JP-A-Heisei 9-237877) is described a semiconductor device. In this reference, a polysilicon film is formed on a substrate, and a doped amorphous silicon is formed on the polysilicon film.
Also, in Japanese Laid Open Patent Application (JP-A-Heisei 9-191092) is described a method of manufacturing a capacitor of a semiconductor device using a polysilicon film. In this reference, an HSG film is used for an electrode. However, the contact hole is not filled with films with different concentrations.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor memory device with a stack electrode in which any defect due to crystallization can be restrained with a low contact resistance and generation of a depletion layer from an HSG grain can be prevented.
Another object of the present invention is to provide a method of manufacturing the above semiconductor memory device.
In order to achieve an aspect of the present invention, a semiconductor memory device includes a source/drain region of a MOS transistor, an interlayer insulating film and a stack electrode section. The source/drain region is formed in a semiconductor substrate. The interlayer insulating film is formed on the semiconductor substrate to cover the source/drain region. The stack electrode section is formed to pass through the interlayer insulating film to the source/drain region, and includes a contact section embedded in the interlayer insulating film and a stack section above the interlayer insulating film, the stack section having an uneven surface portion. An impurity ion concentration of the surface portion of the stack section is higher than that of an inside of the contact section.
An impurity ion concentration of a contact portion contacting the source/drain region of the contact section and the impurity ion concentration of the surface portion of the stack section are higher than that of the inside of the contact section. Also, the impurity ion concentration of the surface portion of the stack section is higher than that of the inside of the contact section and that of the contact portion of the contact section.
Also, the uneven surface portion includes hemi-sphere gains. In this case, the uneven surface portion is connected to a contact portion contacting the source/drain region of the contact section through a portion whose impurity ion concentration is higher than that of the other portion of the stack electrode section. Also, impurity of the surface portion is phosphorus ions or arsenic ions.
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor memory device includes:
forming an inte
Lee Calvin
NEC Corporation
Smith Matthew
Sughrue & Mion, PLLC
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