Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-02-11
2003-01-21
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
Reexamination Certificate
active
06509759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuit protection and more particularly to protection of circuits when more than one power supply is used. Although not limited thereto, the present invention is an improvement on a previous co-pending application filed Sep. 17, 2001, Ser. No. 09/954,251 of Owen Hynes, et al., entitled “High Voltage CMOS Output Driver in Low Voltage Process,” that is assigned to the Assignee of the present invention and is incorporated herein by reference.
2. Description of the Previous Invention
In the above-mentioned co-pending application, a circuit is described which utilizes two voltage sources to supply CMOS transistors in an output circuit that is operable to follow an input voltage at a higher level. More particularly, the invention described provides a high-voltage output buffer implemented in a low-voltage semiconductor process, enabling low-voltage semiconductors to interface with high voltage circuitry. The buffer uses a level translator that changes the input voltage (which, for example, may vary between Vss (for example, ground, or 0 volts), and the voltage of an intermediate source, Vdd, (for example, 3.3 volts), and converts it to an intermediate signal that varies between approximately a reference voltage, Vref, (for example about 1.66 volts), and a high voltage, Vdd
2
, (for example about 5 volts). The buffer also uses an output circuit that changes the intermediate signal to a final signal, which varies between Vss and Vdd
2
(0 to 5 volts). In a preferred embodiment, a first power source, Vdd
2
, supplies the 5-volt signal, a second power source, Vdd, supplies the 3.3-volt signal. The reference voltage, Vref, is derived from the high voltage source so that they both power up at the same time with Vref being about ⅓ of Vdd
2
. The output circuit includes a first P type transistor having a first terminal connected to the high voltage source, Vdd
2
, (5 volts) and a second terminal connected to the first terminal of a second P type transistor. The second terminal of the second P type transistor is connected to the first terminal of a first N type transistor and to the final output line of the circuit. The second terminal of the first N type transistor is connected to the first terminal of a second N type transistor whose second terminal is connected to ground. Thus, the four transistors are connected in series between the high voltage source Vdd
2
(5 volts) and ground. The first P type transistor has it gate connected to the Level Translator to receive a voltage which varies between Vref (1.66 volts) plus a threshold voltage to Vdd
2
(5 volts). The second N type transistor has its gate connected to the Level Translator to receive an inverse of the Input to the Level Translator a signal which varies between ground and Vdd (3.3 volts)
To protect the transistors of the Output Circuit from receiving a voltage in excess of Vdd (3.3 volts) across their terminals, the second P type transistor has its gate connected to Vref (1.66V) and the first N type transistor has its gate terminal connected to Vdd (3.3 V). The Bias provided by the gate voltages (Vref and Vdd) prevents the full voltage, Vdd
2
(5V) to Vss (ground or 0V) from being applied across any two terminals of any single transistor by ensuring that the high voltage drop is shared between the second P type transistor and the first N type transistor. A more complete explanation may be obtained from an examination of the above referred to co-pending application.
There is, however, a possible problem that may arise when the circuit is powered up or when Vdd has a power failure. If, for example, the 5-volt source, Vdd
2
, powers up first and is applied to the four series connected transistors before the 3.3-volt source, Vdd, powers up, an excessive voltage could be applied across a transistor in the output circuit causing damage thereto. Similarly, if Vdd were to drop to zero during a power failure while Vdd
2
was still at a high voltage, an excessive voltage could be applied across a transistor in the output circuit.
It should be understood, that P-type and N-type CMOS transistors may be referred to as PMOS and NMOS transistors respectively herein. Also, CMOS transistors normally have “source,” “drain,” “gate” and “body” terminals. In PMOS transistors, the body terminal is usually tied to the “source” or “drain” whichever is higher while in NMOS transistors, the body terminal is usually tied to the “source” or “drain” terminal whichever is lower. Furthermore, the “source” and “drain” terminals may sometimes change names depending on the connection of the transistors in various configurations. In the present invention, use of “source” and “drain” to identify a particular terminal could become confusing and accordingly these two terminals will just be referred to as “first” and “second” terminals. Thus, the CMOS transistors (including both NMOS and PMOS) will just be recited as having first, second (which may be either drain or source) and gate terminals and the body terminal will be tied to one of the first or second terminals.
SUMMARY OF THE INVENTION
The present invention is an improvement on the above mentioned co-pending application by providing a protective circuit between Vref and the first N type transistor so as to apply the greater of Vdd or Vref to the gate of the first N type transistor in the output circuit. Thus, in the worst case situation, if Vdd is 0 volts, while Vref and Vdd
2
are at their normal value (1.66 volts and 5 volts respectively) as, for example after Vref and Vdd
2
have finished start-up and Vdd has just begun start up, or when Vdd fails, the gate of the first N type transistor is connected to Vref (1.66V) and the maximum voltage across the gate/1st terminal is 3.33 volts (5 volts−1.66 volts) while the voltage across the gate/2nd terminal is 1.66 volts (1.66 volts−0 volts). As Vdd
2
increases, it passes the value of Vref and, and from then on, the Vdd voltage is applied to the gate of the first N type transistor and the voltage across the gate/1st terminal will decrease from 3.33 volts to 1.66 volts (5 volts−3.33 volts) while the voltage across the gate/
2
nd terminal will increase to 3.33 volts (3.33 volts−0 volts) when Vdd reaches its normal value. Thus in no event is the voltage across the gate/either terminal ever greater than 3.33 volts.
REFERENCES:
patent: 5767697 (1998-06-01), Ueno et al.
patent: 5880602 (1999-03-01), Kaminaga et al.
patent: 6346829 (2002-02-01), Coddington
patent: 6351157 (2002-02-01), Sharpe-Geisler
Bremer Dennis C.
Honeywell International , Inc.
Le Don
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