Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-07
2003-04-22
Faburyl, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S358000, C257S359000, C257S360000, C257S361000
Reexamination Certificate
active
06552399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection of integrated circuits, and more particularly to reducing the avalanche breakdown voltage of diodes with shallow trench isolation (STI) in deep-quarter-micron processes.
2. Description of the Related Art
The avalanche breakdown voltage of a diode with shallow trench isolation (STI) has been increased to the level where these devices are no longer effective for ESD protection in deep quarter-micron processes. In this situation, the trigger voltage of the diode is higher than the gate oxide breakdown voltage. Thus, the protection window is zero. Diodes with the STI trigger too high fail when first triggered. The problem stems from the uniform electric field of the n+ junction of a diode which is responsible for the high breakdown, as indicated by Arrow F of FIG.
1
.
FIG. 1
depicts a cross-section of a semiconductor wafer with a p-well
11
having embedded two diodes with a p+ junction
12
each, and having a common n+ cathode
13
. Shallow trench isolations
14
separate the p+ and n+ junctions. Therefore, it is essential to invent a new type of diode with a low and controllable trigger voltage.
U.S. Patents relevant to the subject at hand are listed below.
U.S. Pat. No. 5,708,550 (Avery) discloses an ESD protection structure having a dummy supply line.
U.S. Pat. No. 5,856,214 (Yu) shows a low voltage zener-triggered SCR for ESD.
U.S. Pat. No. 5,850,095 (Chen et al.) teaches an ESD protection circuit using a zener diode and an interdigitated NPN transistor.
U.S. Pat. No. 5,808,342 (Chen et al.) shows a bipolar SCR triggering circuit for ESD protection.
U.S. Pat. No. 5,780,905 (Chen et al.) describes an asymmetrical triggering ESD structure.
It should be noted that none of the above-cited examples of the related art utilize a device with a controllable dummy layer which provides a low controllable trigger voltage and which can be used as a first trigger device in ESD protection networks.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide structures and a method for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks.
Another object of the present invention is to provide a device for ESD protection in deep-quarter micron processes.
A further object of the present invention is to reduce the avalanche breakdown voltage of the device and to make that breakdown voltage readily adjustable to a predetermined low level.
These objects have been achieved by providing a controllable dummy layer diode which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one preferred embodiment of the invention the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second preferred embodiment of the invention the p+ region of the diode is made to overlap the n+ region turning the diode into a zener diode. The low doping channel region under the dummy polysilicon layer functions as a channel stopper and suppresses the occurrence of the leakage current caused by the zener diode. The adjustment of the channel stopper length and the controllable gate voltage enables the controlling of a zener voltage.
REFERENCES:
patent: 5102811 (1992-04-01), Scott
patent: 5708550 (1998-01-01), Avery
patent: 5780905 (1998-07-01), Chen et al.
patent: 5808342 (1998-09-01), Chen et al.
patent: 5850095 (1998-12-01), Chen et al.
patent: 5856214 (1999-01-01), Yu
patent: 6015992 (2000-01-01), Chatterjee et al.
patent: 6417544 (2002-07-01), Jun et al.
patent: 02158127 (1990-06-01), None
Foo Lo Keng
Jun Cai
Chartered Semiconductor Manufacturing Ltd.
Faburyl Wael
Ha Nathan W.
Pike Rosemary L. S.
Saile George O.
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