Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-08
2003-04-01
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C257S751000, C257S757000
Reexamination Certificate
active
06541830
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor fabrication methods and structures resulting from such methods. More particularly, the present invention relates to gate electrode structures and interconnects containing titanium boride and methods for forming such structures.
BACKGROUND OF THE INVENTION
Metal Oxide Semiconductor (MOS) devices are widely used in integrated circuit devices. Such MOS devices may include memory devices which are comprised of an array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. Conductors, referred to as word lines, serve as gate electrodes of multiple access transistors which provide access to the memory cells. In a DRAM (Dynamic Random Access Memory), a word line gate electrode typically is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide, known as the gate oxide. Word lines conventionally are formed on the gate oxide layer as a two-layer stack, typically including polysilicon and a conductor material such as tungsten silicide or titanium silicide (commonly referred to as a polycide word line). Further, polycide structures are also used for local interconnects in MOS devices. For example, such polycide structures may be used or the local interconnection of gates and drains in a SRAM (Static Random Access Memory).
Minimizing resistivity throughout the word line or other interconnect structures is of importance to meet the need of reducing time constants and allowing access of memory cells in as short a time period as possible. As memory density increases, feature sizes, including line sizes, decrease. For example, when the feature size of a conductor, such as a local interconnect or a word line, is reduced in a high density memory, the resistance of the conductor increases. Thin tungsten silicide and titanium silicide are larger grain materials that contribute to a very rough silicide/silicon interface. As such, it reduces the effective ohmic contact area. Therefore, it is desirable to utilize conductors whose resistivity will not significantly increase for the same feature dimensions.
Further, in the fabrication of semiconductor devices, it is desirable to find conductors which are suitable for use at high temperatures (e.g., up to a out 1100° C.) during processing steps. Particularly desirable are materials which have low bulk resistivities and good oxidation resistance at high temperatures. However, such materials can be difficult to find, and, once found, difficult to form by conventional methods. Further, other problems may occur with such materials, such as, for example, diffusion of atoms from one layer to another, particularly at high processing temperatures. Such diffusion is particularly undesirable if the properties of one layer are changed because of diffusing atoms.
It has been reported in the article by Choi et al., “Electrical Characteristics of TiB
2
for ULSI Applications,” IEEE Transactions on Electron Devices, Vol. 39, No. 10 (October 1992) that titanium diboride may be used as a diffusion barrier in metallization applications.
In view of the above, there is a need for low resistivity material for use in gate electrode and interconnect applications. The present invention provide gate electrode structures and interconnect structures which overcome the disadvantages described above, along with other problems as will be apparent from the description below.
SUMMARY OF THE INVENTION
A method for use in the fabrication of a gate electrode according to the present invention includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer.
In one embodiment of gate electrode formation method, a barrier layer is formed on the oxide layer prior to forming the titanium boride layer. The barrier layer is formed of a material selected from refractory suicides and refractory nitrides. Further, the gate electrode is formed from the barrier layer and the titanium boride layer.
In another embodiment of the gate electrode formation method, a polysilicon layer is formed on the gate oxide layer prior to forming the titanium boride layer. The gate electrode is then formed from the titanium boride layer and the polysilicon layer.
In yet another embodiment of the gate electrode formation method, a polysilicon layer is formed on the gate oxide layer and a barrier layer is formed on the polysilicon layer prior to forming the titanium boride layer. The barrier layer is formed of a material selected from refractory silicides and refractory nitrides. Further, the gate electrode is formed from the polysilicon layer, the barrier layer, and the titanium boride layer.
A method for use in the formation of an interconnect in the fabrication of integrated circuits is also described. The method includes providing a substrate assembly including at least two contact regions. A titanium boride layer is formed on the substrate assembly. The interconnect is then formed from the titanium boride layer to connect the at least two contact regions.
In one embodiment of the interconnect formation method, a polysilicon layer is formed on the substrate assembly prior to forming the titanium boride layer. The interconnect is then formed from the titanium boride layer and the polysilicon layer.
In another embodiment of the interconnect formation method, the method includes forming a barrier layer on the substrate assembly prior to forming the titanium boride layer. The barrier layer is formed of a material selected from refractory silicides and refractory nitrides. Further, the interconnect is then formed from the barrier layer and the titanium boride layer.
In yet another embodiment of the interconnect formation method, a polysilicon layer is formed on the substrate assembly and a barrier layer is formed on the polysilicon layer prior to forming the titanium boride layer. The barrier layer is formed of a material selected from refractory suicides and refractory nitrides. Further, the interconnect is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.
A method of depositing a titanium boride layer for use in the fabrication of integrated circuits according to the present invention includes providing a chemical vapor deposition reaction chamber containing a substrate assembly. Reactive compounds of titanium, boron and silicon are provided in the reaction chamber. A titanium silicide boride layer is then formed on the substrate assembly by chemical vapor deposition.
A gate electrode structure according to the present invention includes a substrate assembly having a gate oxide region formed thereon. A titanium boride region is formed on the gate oxide region and a cap region is formed on the titanium boride region.
In one embodiment of the gate electrode structure, the a polysilicon region is formed between the gate oxide region and the titanium boride region.
In another embodiment of the gate electrode structure, a barrier region is formed between the polysilicon region and the titanium boride region. The barrier region is formed of a material selected from refractory silicides and refractory nitrides.
In yet another embodiment of the gate electrode structure, a barrier region is formed between the gate oxide region and the titanium boride region. The barrier region is formed of a material selected from refractory silicides and refractory nitrides.
An interconnect structure according to the present invention is also described. The structure includes a substrate assembly including at least two contact regions. A titanium boride region is formed on the substrate assembly connecting the at least two contact regions.
In one embodiment of the interconnect structure, a polysilicon region is formed between the substrate assembly and the titanium boride region.
In another embodiment of the interconnect structure, a barrier region is formed betwe
Booth Richard
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
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