Semiconductor device and method for fabricating the same

Details Semiconductor device and method for fabricating the same Semiconductor device and method for fabricating the same

2000-01-13

2003-07-22

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S289000, C257S371000

Reexamination Certificate

active

06597016

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device functioning as a field effect transistor including a heterojunction and a method for fabricating the same.
Radio frequency (RF) semiconductor devices have heretofore been fabricated using a substrate made of a compound semiconductor like GaAs. Recently, however, technology of fabricating RF semiconductor devices using a novel mixed crystal semiconductor, which is much more compatible with a silicon process, has been researched and developed. Among other compounds, silicon germanium, which is expressed by a chemical formula Si
1−x
Ge
x
(where x is a mole fraction of Ge), is highly compatible with a silicon process in view of the fabrication technology applicable thereto. Thus, if Si
1−x
Ge
x
is used, then it is possible to take full advantage of richly cultivated silicon processing technology. In addition, SiGe and silicon (Si) together form a heterojunction therebetween. Thus, by utilizing the variability of its composition Si
1−x
Ge
x
(where 0<x<1) and the strain caused around the heterojunction, any device can be designed freely. Furthermore, carriers can move at a higher mobility in an SiGe layer than in an Si layer. Accordingly, a semiconductor device including an SiGe layer can operate faster with reduced noise. Paying special attention to the advantages of SiGe such as these, bipolar transistors and field effect transistors with an Si/SiGe heterojunction have been proposed, modeled and used practically.
For example, Solomon et al. of IBM Corp. proposed a heterojunction MOS transistor (HMOS transistor) including an Si—Ge layer as disclosed in Japanese Laid-Open Publication No. 3-3366. In this specification, the HMOS transistor of Solomon et al. will be labeled as first prior art example for convenience sake.
FIG.
13
(
a
) is a cross-sectional view illustrating a structure of such an HMOS transistor according to the first prior art example. FIG.
13
(
b
) is a cross-sectional view illustrating the region R
50
a
shown in FIG.
13
(
a
). FIG.
13
(
c
) is a cross-sectional view illustrating movement, diffusion and segregation of Ge atoms after the HMOS transistor of the first prior art example, including a thin Si cap layer, has been annealed. And FIG.
13
(
d
) is a cross-sectional view illustrating movement, diffusion and segregation of Ge atoms after the HMOS transistor of the first prior art example, including a thick Si cap layer, has been annealed. Only the region R
50
b
shown in FIG.
13
(
b
) is illustrated in FIGS.
13
(
c
) and
13
(
d
).
As shown in FIG.
13
(
a
), the HMOS transistor includes: Si substrate
501
; p
+
-type polysilicon gate electrode
516
; SiO
2
layer
517
; intrinsic (i-) Si
1−y
Ge
y
layer
519
(where y is a mole fraction of Ge); i-Si cap layer
542
; source contact
551
connected to a source region
553
; and drain contact
552
connected to a drain region
554
. In FIG.
13
(
a
), the SiO
2
/Si and Si/Si
1−y
Ge
y
interfaces are identified by the reference numerals
535
and
536
, respectively.
The HMOS transistor shown in FIGS.
13
(
a
) through
13
(
c
) is a p-channel MOS transistor. The source/drain regions
553
and
554
and the gate electrode
516
thereof are in similar shapes to those of an ordinary Si MOS transistor. But the p-channel is formed within Si
1−y
Ge
y
layer
519
to further increase the conductivity thereof. The atomic radius of Ge atoms
506
is greater than that of Si atoms. Thus, the i-Si
1−y
Ge
y
layer
519
receives a compressive strain because there is a lattice misfit between the i-Si
1−y
Ge
y
layer
519
and the Si substrate
501
. Generally speaking, a phenomenon relaxing compressive strain is likely to occur during an epitaxy. Thus, it is not easy to stack the Si and SiGe layers consecutively while maintaining the crystallinity thereof. However, if the i-Si
1−y
Ge
y
layer
519
is deposited to a critical thickness thereof or less, then no dislocations, which ordinarily relax the strain, are brought about near the Si/Si
1−y
Ge
y
interface
536
. As a result, these layers
519
and
542
can be stacked one upon the other in an equilibrium state with the crystallinity thereof maintained. In general, strain changes a band structure and the carrier mobility of holes. In an Si/Si
1−y
Ge
y
heterojunction device, however, if the Ge mole fraction y is adjusted within such a range as not causing the dislocations, then the band offset around the interface can be optimized thanks to the compressive strain and the mobility of holes can be increased. That is to say, as shown in FIG.
13
(
b
), the holes can be confined in a heterobarrier by utilizing the offset at the valence band in the Si/Si
1−y
Ge
y
heterojunction device. Accordingly, the Si/Si
1−y
Ge
y
heterojunction device is applicable as a heterojunction PMOSFET. When a negative voltage is applied to the gate electrode
516
, the polarity of the regions surrounding the Si/Si
1−y
Ge
y
interface
536
is inverted, thus forming a p-channel, where positive carriers (holes) are confined, along the Si/Si
1−y
Ge
y
interface
536
. As a result, those carriers travel at a high velocity from the source region
553
toward the drain region
554
. In this case, if the Si/Si
1−y
Ge
y
interface
536
is planar, then the p-channel is formed along the planar Si/Si
1−y
Ge
y
interface
536
, and therefore, the carriers can move at an even higher velocity.
As can be seen, a field effect transistor using SiGe can operate faster than a field effect transistor using Si.
Ismail proposed a heterojunction CMOS transistor in 1995 IEEE IEDEM Tech. Dig. 509 (see also M. A. Armstrong, D. A. Antoniadis, A. Sadek, K. Ismail and F. Stern, 1995 IEEE IEDEM Tech. Dig. 761 and Japanese Laid-Open Publication No. 7-321222). In this specification, this HCMOS transistor will be labeled as second prior art example for convenience sake.
FIG.
14
(
a
) is a cross-sectional view illustrating a semiconductor device according to the second prior art example. FIG.
14
(
b
) illustrates a vertical cross section of a region including gate electrode, gate insulating film and channel in the PMOS
530
or NMOS transistor
531
shown in FIG.
14
(
a
). On the left-hand side of FIG.
14
(
b
), shown is a valence band corresponding to a negative gate bias voltage applied. On the right-hand side of FIG.
14
(
b
), shown is a conduction band corresponding to a positive gate bias voltage applied. FIG.
14
(
c
) is a cross-sectional view of the region R
60
b
shown in FIG.
14
(
b
) illustrating movement and segregation of Ge atoms after the HCMOS transistor of the second prior art example has been annealed. As shown in FIG.
14
(
a
), the HCMOS transistor includes Si substrate
501
, PMOSFET
530
, NMOSFET
531
, n-well
532
and shallow trench isolation (STI) region
534
. As shown in FIG.
14
(
b
), Si
1−x
Ge
x
buffer layer
523
, i-Si
1−x
Ge
x
spacer layer
521
, &dgr;-doped layer
522
, i-Si layer
520
, i-Si
1−y
Ge
y
layer
519
, i-Si layer
518
, SiO
2
layer
517
and polysilicon gate electrode
516
are stacked in this order. In FIG.
14
(
b
), first, second and third interfaces are identified by the reference numerals
537
,
538
and
539
, respectively.
In the example illustrated in FIG.
14
(
a
), an HCMOS device is made up of n- and p-channel field effect transistors each including the Si
1−y
Ge
y
layer
519
. According to this prior art example, superior conductivity is attainable compared to a homojunction transistor formed on an Si substrate. In addition, since the n- and p-channel MOS transistors are formed using a common multilayer structure, the fabrication process thereof is simpler.
As shown in FIG.
14
(
b
), strain can be relaxed by the Si
1−x
Ge
x
buffer layer
523
, on which the i-Si
1−x
Ge
x
(where x=0.3) spacer layer
521
is formed. The &dgr;-doped layer
522
for supplying carriers to the n-channel is defined within the i-Si
1&minus

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