Cache memory array for multiple address spaces

Details Cache memory array for multiple address spaces Cache memory array for multiple address spaces

2000-06-16

2003-05-27

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

06571316

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer memory systems and, more particularly, to processor cache circuitry which stores information from multiple address spaces.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but very fast host processor (called a “morph host”) and software (called “code morphing software”) to execute application programs designed for a processor having a different instruction set at a rate equivalent to that of the processor for which the programs were designed (the target processor). The morph host processor executes the code morphing software to translate the application programs into morph host processor instructions which accomplish the purpose of the original target software. As the target instructions are translated, they are stored in a translation buffer where they may be accessed without further translation. The resulting translations are then executed and perform the same functions that they would on a processor that implemented the target architecture in hardware. Although the initial translation and execution of a program may be slow, once translated, many of the steps normally required to execute a program in hardware are eliminated. The new processor is described in detail in U.S. Pat. No. 6,031,992, entitled
Combining Hardware And Software To Provide An Improved Microprocessor
, Cmelik et al, issued Feb. 29, 2000, and assigned to the assignee of the present application.
In order to carry out its operations, the host processor must be able to access two different types of memory, host memory and target memory. The instructions executed by the morph host, including both the code morphing software which accomplishes the translations and the translations themselves, reside in host memory. The target instructions and data manipulated by the target instructions reside in target memory.
During the translation process, code morphing software must manipulate various kinds of data including, among other things, data related to the translations and the state of the target program. In addition, code morphing software uses numerous data structures to perform various optimizations on the translated instructions. This data also resides in host memory.
To prevent corruption of code morphing software state, the target program must be kept from reading or writing host memory. The host processor must therefore be able to distinguish between host and target memory as two different “address spaces.” Distinguishing between these address spaces is not possible utilizing techniques known to the prior art because prior art processors do not dynamically translate instructions from a target to a host instruction set and therefore do not utilize these different memory spaces.
Like other processors, the host processor includes a cache which enhances performance by storing a copy of frequently accessed memory locations that can be read and written much more quickly than external memory. The cache has much smaller capacity than main memory because it is physically located on the processor rather than on external memory chips. Since the host processor must access both host and target memory, its cache must also be able to access both host and target memory.
During the translation process, a need for local or “scratch memory” to assist with the translation process also arises. The translation process creates a significant amount of non-permanent state. The translation process also requires information about the state of the target program which may be frequently accessed. Typically, such information would be placed in processor registers. However, the translation process requires various data structures and other larger groups of information which cannot be conveniently stored in registers but should be available more rapidly than access to system memory provides.
It is therefore desirable to provide improved processor caches and arrangements for accessing processor caches and local memory utilized by a processor.
SUMMARY OF THE INVENTION
The present invention is realized by apparatus including a cache having a plurality of storage positions for data and for addresses, each of the storage positions including positions signifying one of a plurality of address spaces; and selection circuitry selecting data from a storage position based on an address including an address space indicator.


REFERENCES:
patent: 5768593 (1998-06-01), Walters et al.
patent: 5809522 (1998-09-01), Novak et al.
patent: 6298411 (2001-10-01), Giacalone
patent: 6430674 (2002-08-01), Trivedi et al.
patent: 6470492 (2002-10-01), Bala et al.

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