Method for fabricating polycide dual gate in semiconductor...

Details Method for fabricating polycide dual gate in semiconductor... Method for fabricating polycide dual gate in semiconductor...

2000-12-14

2003-03-04

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S585000, C438S590000, C438S682000, C438S683000, C438S685000, C438S655000, C438S656000, C438S657000, C438S660000, C438S663000, C438S664000, C438S227000, C438S199000, C438S229000

Reexamination Certificate

active

06528401

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device.
2. Background of the Related Art
A related art dual gate in a semiconductor device will now be described. FIGS.
1
A~
1
E illustrate sections showing the steps of a related art method for fabricating a dual gate.
As shown in
FIG. 1A
, the related art method for fabricating a dual gate starts with forming device isolating layers
2
in device isolating regions of a semiconductor substrate
1
by LOCOS or STI. N type and P type impurity ions are implanted in active regions defined by the device isolating regions
2
to form P type well region
3
and N type well region
4
. Then, a gate oxide film
5
, and an undoped polysilicon layer
6
as a gate forming material layer are formed on an entire surface inclusive of the P type well region
3
and the N type well region
4
. A photoresist film is coated on an entire surface, and selectively patterned, to form a first photoresist film pattern layer
7
. The first photoresist film pattern layer
7
is used as a mask in implanting ‘n’ type impurity ions in an exposed surface of the undoped polysilicon layer
6
. The ‘n’ type impurity ion implantation forms an ‘n’ type impurity implanted layer
6
a
on the P type well region
3
.
As shown in
FIG. 1B
, the first photoresist film pattern layer
7
is removed. A photoresist film is coated again, and selectively removed to leave the photoresist film only on the P type well region
3
, which forms a second photoresist pattern layer
8
. The second photoresist pattern layer
8
is used as a mask in implanting ‘p’ type impurity ions in an exposed surface of the undoped polysilicon layer
6
. The ‘p’ type impurity ion implantation forms a ‘p’ type impurity implanted layer
6
b
on the N type well region
4
.
As shown in
FIG. 1C
, a barrier layer
10
of a tungsten silicide or tungsten, and a hard mask layer
11
for gate patterning are formed on the ‘n’ type impurity implanted layer
6
a
and the ‘p’ type impurity implanted layer
6
b.
The hard mask layer
11
for gate patterning is formed of an oxide or a nitride. Then, a photoresist film is coated on the hard mask layer
11
and selectively patterned to form a third photoresist film pattern layer
9
As shown in
FIG. 1D
, the third photoresist film pattern layer
9
is used as mask in selectively patterning exposed portions of the hard mask layer
11
for gate patterning, which is used as a hard mask in selectively etching the barrier layer
10
, and the polysilicon layers
6
a
and
6
b
to form gates
12
a
and
12
b.
As shown in
FIG. 1E
, an oxide or nitride film is deposited on an entire surface inclusive of the gates
12
a
and
12
b,
and subjected to anisotropic etching to form sidewalls
13
at sides of the gates. Though not shown on the drawing, photoresist film mask patterns are alternatively formed on the P type well
3
and the N type well
4
to implant n type impurities in the P type well region
3
by using the gate
12
a
as a mask to form source/drain regions
14
a,
and to implant p type impurities in the n type well region
4
by using the gate
12
b
as a mask to form source/drain regions
14
b.
Thus, by forming an n-polygate and a p-polygate on one wafer in the same process, fabrication of a logic circuit is made simple.
As described above, the related art method for fabricating a dual gate has various disadvantages. Since the dual gate is formed by implanting impurity ions using a single polysilicon layer, the gate short channel effect caused by employment of a buried PMOS, if a PMOS is required, for optimization of device performances impedes formation of a device having a gate length below 0.25 &mgr;m. Further, the formation of two sheets of masks required after deposition of the polysilicon layer and in the formation of the source/drain in fabrication of the dual gate (i.e., for providing an n-poly in an NMOS, and a p-poly in a PMOS) leads to additional fabrication steps that increase production costs. The implantation of ions in the polysilicon layer can damage the gate oxide film if the polysilicon layer is thin (below 500 Å), which impedes a regular fabrication because too low an energy should be used in implanting ions in formation of p
+
poly. Since it is impossible to drop a sheet resistivity below 10 &OHgr;/m even if the tungsten silicide is deposited to a thickness greater than than 1000 Å as the tungsten silicide has at best a resistivity in a range of 100 &mgr;&OHgr;m, the tungsten silicide is not suitable for use as a barrier layer. If a tungsten layer, not the tungsten silicide layer, is used to reduce the resistance, an additional diffusion barrier of TiN or WN is required to prevent a reaction with silicon. Also, a re-oxidation is required for restoring the damage to the gate oxide film from the etching since the tungsten is vulnerable to reaction with oxygen, which causes selective oxidation. However, the selective oxidation has difficulty in process control that deteriorates reproducibility. See S. Iwata et al., IEEE Trans. Elec. Dev. ED-31, 1174 (1984). The re-oxidation causes a problem of oxidizing the polycide. See M. Tanielian et al., IEEE Tran. Elec. Dev. Lett. EDL-6, 221 (1985), and K. A. Jenkins et al., Tech. Dig Int. Elec. Dev. Meet., 891(1993).
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that substantially obviates one or more problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device having a dual gate of cobalt polycide.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that has an excellent thermal stability and a low resistance.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that can be patterned using a time and cost efficient fabrication process.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that has a reduced gate length below 0.25 &mgr;m.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that implants source/drain regions concurrently with gate ions.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that diffuses ions into a silicide layer to reduce a thickness of a polysilicon layer.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that can eliminate a low energy ion implanting equipment from a fabrication process.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that has a low resistivity without a diffusion prevention layer in the gate electrode.
Another object of the present invention is to provide a method for fabricating a polycide dual gate in a semiconductor device that reduces oxidation damage to a polycide layer.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a polycide dual gate in a semiconductor device includes (1) forming polysilicon pattern layers on a first and a second regions of a semiconductor substrate, (2) forming a b

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