Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2000-03-13
2003-03-18
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
Reexamination Certificate
active
06536001
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to high speed data communications wherein signal information is processed both in digital and analog forms. More specifically, the invention is related to both a system and method that uses a single modulo operation to achieve maximum system performance in the form of data throughput in digital subscriber line modems that use convolutional interleaving to buffer the effects of burst errors in the data transmission channel.
2. Discussion of the Related Art
In recent years, telephone communication systems have expanded from traditional plain old telephone system (POTS) communications to include high-speed data communications as well. As is known, POTS communications include the transmission of voice information, control signals, public switched telephone network (PSTN) information, as well as, information from ancillary equipment in analog form (i.e. computer modems and facsimile machines) that is transmitted in the POTS bandwidth.
Prompted largely by the desire of large businesses to reliably transfer information over a broadband network, telecommunications service providers have employed digital subscriber lines (DSL) to provide a plethora of interactive multi-media digital signals over the same existing POTS twisted-pair lines.
The provision of DSL services to customer premises has proliferated over recent years. DSL services are typically provided to remotely located customer premises by equipping both the appropriate central office and the customer premises with compatible DSL modems. DSL modems communicate by modulating a baseband signal with customer desired service signals, converting the modulated digital data signal to an analog signal, and transmitting the analog signal over the conventional copper wire pair provided in the PSTN from a central office to a customer premises via a carrier service area (CSA) loop. Well known data modulation and transmission techniques include mapping digital data to be transmitted into a multi-dimensional multi-level signal space constellation and decoding the received constellation to recover the transmitted information.
DSL modems use a number of different modulation schemes and rates. Asymmetric digital subscriber line (ADSL) systems adopted discrete multi-tone (DMT), a rate adaptive and tone flexible multi-carrier data transmission method. DMT systems, by nature of their distribution across multiple frequency bands, are capable of retuning modems to optimize data transfer for changing line conditions. DMT devices selectively transfer bits from the data stream in those discrete frequency bands that are uncorrupted from amplitude modulation radio interference and unaffected by phone system bridge taps, thereby tuning, or maximizing performance under changing line conditions.
To accommodate maximum flexibility for providers and end users of ADSL services, forward error correction (FEC) is selectively applied to the composite data streams to, or from, the central office ADSL modem. This permits FEC to be included or excluded on a data service by data service basis within the composite data stream.
As an example of the mixed requirements for FEC in an ADSL service, consider transmitting a one-way data stream from the central office to a remote unit along with a bi-directional channel. The end user may require high reliability on the one-way channel because the channel may contain highly compressed digital data with no possibility for requesting retransmission. For this portion of the composite data stream, FEC is necessary. On the other hand, voice services and duplex data services with their own embedded protocols may require minimum latency. For this portion of the composite data stream, FEC is optional.
FEC involves the addition of redundant information to the data to be transferred. The data to be transferred along with the redundant data when added together form what are commonly known as codewords. FEC in ADSL employs Reed-Solomon codes based on symbols of 8 bits to a byte. That is, a code over the Galois Field (2
8
). FEC in ADSL is rate adaptable providing for various interleave depths and codeword lengths to support a range of data rates while maintaining constant interleave latency. An enhancement to FEC involves shuffling or interleaving the encoded data prior to transmission, then unshuffling or deinterleaving the data received at the remote DSL modem. Interleaving ensures that bursts of error noise during data transmission do not adversely affect any individual codeword in the transmission. If noise affects a particular frame of data, only a minimum number of bytes of any particular codeword will be affected as the individual codewords are distributed across multiple frames.
The combination of Reed-Solomon encoding with data interleaving is highly effective at correcting errors caused by impulse noise in the service subscriber's local loop. In convolutional interleaving, after writing a byte into interleave memory, a previously written byte is typically read from the same memory.
Standard T1.413, Interface between Networks and Customer Installation—ADSL Metallic Interface provides for convolutional interleaving/deinterleaving along with Reed-Solomon coding as part of forward error correction (FEC). The standard provides an effective method for dealing with burst error channels in modern telecommunication systems. In DMT systems, two latency channels are supported: interleave data and fast data (without interleaving). Convolutional interleaving/deinterleaving is typically implemented by processing the Reed-Solomon encoded digital data sequence through a linear finite state shift register. In high bit rate applications like DMT, a random access memory (RAM) device may be used as the data storage means. Convolutional interleaving/deinterleaving is computation intensive. In software approaches that use a single address pointer and several modulo and addition operations to update the address pointer, system level concurrency and performance is adversely affected. Conversely, hardware approaches that utilize multiple pointers for interleaving/deinterleaving operations increase the complexity of the overall DSL system. The system performance trade-off introduced by FEC in the form of Reed-Solomon coding and convolutional interleaving can be described as increased data transmission reliability at the expense of increased channel latency. U.S. Pat. No. 5,764,649 to Tong introduced a method for efficient address generation for convolutional interleaving. The method taught in the '649 patent is a multi-step computation intensive process for minimizing the amount of memory required. The '649 patent requires many cycles and instructions to read and write interleaved data. As a result, data transmission is delayed for convolutional data interleaving.
SUMMARY OF THE INVENTION
In light of the foregoing, the invention is a circuit and method that provides a one-step real time pointer for interleaving/deinterleaving that uses a single modulo operation. The single modulo pointer of the present invention may be used to increase data throughput through an interleaver/deinterleaver.
To achieve the objects and advantages of the present invention, the present invention is directed to a circuit and method for implementing an addressing pointer that permits the integration of both fast path and interleaved data in a memory device at the rate encoded data is provided. Similarly, the stored fast path and interleaved data may then be read from the memory device at the rate requested by the next data processing device, i.e., tone ordering and symbol generator, by using a similarly configured addressing pointer. The circuit and method of the present invention is applicable in the receive data path as well. Received data symbols are processed by a demapper before being sent to deinterleave memory. As in the transmit data path, data from the demapper is applied to deinterleave memory at the rate provided by the demapper. The integrated fast path and
Cai Lujing
Pan Wenwei
Wang Jian
Baker Stephen M.
Globespanvirata, Inc.
Thomas Kayden Horstemeyer & Risley
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