Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-11-15
2003-05-06
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S754000
Reexamination Certificate
active
06559062
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of micro-electronics, and more specifically to a method for forming a sub-micron sized interconnect on a semiconductor wafer, and specifically to an improved etching procedure for avoiding the formation of a notch in a metal layer masked with a photoresist layer having a thickness of no more than 0.66 microns.
BACKGROUND OF THE INVENTION
There is a continuing demand in the semiconductor industry for lower cost and improved reliability. The ability to create semiconductor devices with sub-micron sized features has greatly reduced the cost and improved the reliability of current devices when compared to similar devices produced just years ago. Smaller features result in a decrease in performance degrading capacitances and resistances and allow more devices to be formed on a single semiconductor wafer. However, the continued reduction in the size of the interconnections between the various active devices on a semiconductor wafer (interconnects) can result in an adverse electrical effect. Although the resistance of metal interconnects is reduced by a decrease in the length of the metal run, a reduction in the width and/or thickness of the interconnect structure will result in a corresponding increase in resistance per unit length, as well as an increased risk of electo-migration failures due to the higher current density carried by the narrower, thinner metal line. Thus, the designer of a very large scale integration (VLSI) device must carefully balance the advantages and disadvantages of continued reduction of the interconnect dimensions.
Continued reduction of dimensions in semiconductor devices have been made possible, in part, by advances in lithography, such as the use of more advanced cameras and the development of more sensitive photoresist materials. However, the accuracy of the lithographic pattern must then be reproduced onto the semiconductor. The use of reactive ion etching (RIE) has allowed the industry to transfer very small images in photoresist to an underlying metal layer. RIE removes material by exposing a surface to a combination of chemical etchants and a stream of plasma ions. In order to control the slope of the resulting metal layer side surface, it is desirable to have as thin a layer of photoresist as possible, limited however, by the relative removal rates of the masking photoresist and the exposed metal layer.
FIG. 1
illustrates a prior art semiconductor device
10
at a selected stage of a manufacturing process. Device
10
includes a semiconductor wafer such as silicon (Si) wafer
12
having an active device region such as silicon dioxide (SiO
2
) layer
14
formed therein. A metal layer such as aluminum copper (AlCu) layer
16
is disposed over the silicon dioxide layer
14
, and is shown in
FIG. 1
has having been partially removed by etching to form an interconnect structure
18
. The width of interconnect
18
is defined by the width W of a photoresist layer
20
disposed over the metal layer
16
. The aluminum copper layer
16
is separated from the silicon dioxide layer
14
by a titanium (Ti) layer
22
disposed on the silicon dioxide layer
14
and a first titanium nitride (TiN) layer
24
disposed on the titanium layer
22
. In order to eliminate problems associated with back reflection of light during the photo-lithography process, it is known to form an anti-reflective coating (ARC) layer between the photoresist layer
20
and the metal layer
16
. A second titanium nitride layer
26
and a layer of silicon oxy-nitride (SiON)
28
interact to function as an anti-reflective coating layer
27
.
The materials and dimensions of device
10
and the processes used to manufacture such a structure are known in the art. For example, the aluminum copper material of metal layer
16
may range from about 0-1% copper, and may be deposited by known processes such as physical vapor deposition (PVD) to a thickness from 5,000-7,000 Angstroms. The titanium and titanium nitride barrier layers
22
,
24
,
26
may be deposited by PVD or chemical vapor deposition (CVD) to a thickness of 300-500 Angstroms. The ARC layer
28
may be deposited by CVD or plasma enhanced CVD to a thickness of 300-350 Angstroms. Portions of the barrier layers
28
,
26
,
24
,
22
and metal layer
16
are removed by an RIE process to form the interconnect
18
corresponding to the pattern formed in the photoresist layer
20
.
A prior art recipe
40
for an RIE process for forming interconnect
18
is illustrated in FIG.
2
. The recipe
40
includes the various steps shown in column
42
in the order taken, along with the respective flow rates of etchant gasses Cl
2
, BCl
3
, and passivation gas CHF
3
shown in scc/min in the respective columns
44
,
46
,
48
. The gas pressure present in the reactor during the respective step is shown in millitorr units in column
50
. The source power and bias power applied during the respective steps are shown in watts in columns
52
,
54
respectively. The pressure of helium cooling gas supplied to the reverse side of the wafer
12
is shown as a constant 10 torr in column
56
. Finally, the duration of each respective step is shown in seconds in column
58
.
As shown in
FIG. 2
, the prior art RIE process begins with an etch step
60
10
lasting thirty seconds for removing the ARC layer
27
. The Cl
2
gas acts as the etchant as the layers of material
28
,
26
are removed by high energy ions. The flow of CHF
3
acts as a passivation gas during this step. Passivation is a concept known in the art for depositing a buffer layer on the surfaces of a material being exposed to a reactive ion etch. As the horizontal surface of the material is removed by the combination of chemical and sputtering effects generated by the vertically oriented ions produced in the RIE process, the newly exposed side vertical surface is protected from the ion stream by the overlying masking layer. However, the newly exposed vertical surfaces continue to be exposed to the effects of the chemical etchants. This isotropic chemical effect results in the undesirable removal of material in the horizontal direction during the desirable removal of material in the vertical direction. Passivation gasses supply a layer of protective material to the newly exposed vertical surfaces to retard the isotropic effect, thereby limiting the removal of material in the horizontal direction. A common passivation gas is CHF
3
which is generally understood to provide a source of carbon that is deposited on the vertical surfaces of the metal layer being etched and which serves as a buffer against the continued corrosion of material in the horizontal direction. Without such passivation, an etched metal line may form as a trapezoid rather than the desired rectangular cross-sectional shape.
The ARC layer etch step
60
is followed by a fifteen second break through etch step
62
, during which the flow of passivation gas is stopped. It is known in the art that the uppermost portion of a metal layer such as layer
16
will be more resistive to an etching process than will be the remainder of the layer. It is believed that a small amount of corrosion products may accumulate on the top surface of a metal layer during the processing of the device, thereby creating a thin interface layer
29
, perhaps less than 100 Angstroms thick, that becomes more resistive to etching. Break through etch step
62
utilizes a significantly higher flow rate of BCl
3
than the other etch steps. In addition, the bias power level
54
is also significantly increased to provide a higher energy level to the etching ions. Moreover, the flow of passivation gas is preferably stopped in order to improve the removal rate, to improve the control of the resulting geometry, and for chamber cleanliness considerations.
A main metal etch step
64
is then performed for a duration EP, which may be approximately 60 seconds for example, to remove the remaining thickness of the metal layer
16
. Strategies for determining the appropriate time to end this step are well known in
Downey Stephen Ward
Murphey Paul B.
Wolf Thomas Michael
Yen Allen
Agere Systems Inc.
Chaudhuri Olik
Maire David G.
Pham Thanh
Reusse Brownlee Bowdoin & Wolter, P.A.
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