Row decoder for a nonvolatile memory device

Details Row decoder for a nonvolatile memory device Row decoder for a nonvolatile memory device

2001-08-06

2003-07-01

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185230

Reexamination Certificate

active

06587375

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-45687, filed on Aug. 7, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a nonvolatile memory device and more particularly to a row decoder employed in the non-volatile semiconductor memory device.
BACKGROUND OF THE INVENTION
Generally, semiconductor memory devices for storing data are classified into volatile and non-volatile, the latter class including flash memory devices. In a flash semiconductor memory device its memory cells can be electrically programmed and data stored in the memory cells can be electrically erased. According to an operation of a normal flash memory device, programming of the memory cells is conducted by using the injection of hot electrons to a floating gate from a drain region and an adjacent channel region. To program the cells, a voltage of about 5V is applied to the drain region to generate hot electrons while a source region and a substrate (or a bulk) are grounded in common, and a high voltage of about 9V is applied to a control gate. As such, since the floating gate in the programmed memory cells is filled with negative charges, a threshold voltage of the memory cells is increased. To the contrary, to erase the cells, a negative high voltage of −9V is applied to the control gate while a counter voltage about 9V is applied to the bulk region, thereby causing migration of the negative charges from the floating gate to the bulk region (Fouler-Nordheim Tunneling). The threshold voltage of the memory cells whose data are erased becomes lower than those of the memory cells not erased. In a read-out operation, a voltage of about 1V is applied to the drain region, a lower voltage than a threshold voltage of the programmed memory cell also is applied to the control gate and at the same time 0V is applied to the source region so that the programmed memory cell is an “off-cell” and the erased memory cell is an “on cell”.
When a read-out operation on the programmed memory cells or the memory cells whose data are erased is to be performed, a voltage between the threshold voltage of a programmed memory cell and that of a data erased memory cell is applied to a word line connected to a selected memory cell. One approach to resolve the problem whereby the read-out voltage is higher than a voltage of a power supply, boosting the read-out voltage is described in “A 2.7V only 8 Mb×16NOR flash memory”, symposium on VLSI Circuits Digest of Technical Papers, IEEE 1996.
Recently there is a need for reducing power consumption in the flash memory used in devices such as a handheld communications device or a portable computer operated by a battery. However, the largest obstacle for lowering a used voltage together with very large scale integration (VLSI) is this: The larger the degree of integration, the lower the coefficient of the boosting voltage in the word line during a low-voltage read-out operation.
Some methods for solving this problem have ever been introduced. One of the methods is a process for multi-boosting the word line that enables the fast, low-voltage, read-out operation by increasing the coefficient of the boosting voltage. See (“Quick Double Bootstrapping Scheme for Word Line of 1.8V Only 16 Mb Flash Memory”, the sixth Korean Semiconductor conference, February, 1999). Another is a process in which a charge pump, i.e., a high voltage generator, can be driven on being powered up, so that when a read-out operation is started a high voltage generated from the charge pump can be applied to word lines. This process recently becomes popular in use, since the process enables fast operational speed and lowers power consumption. See (“On-chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier technique”, J. F. Dickson, IEEE Journal of Solid State Circuits, Jun 1976, pages 374-378). The technologies that use the charge pump to boost the voltage of the word lines on a read-out operation under the low-power voltage are described in an “Optimization of word-line booster circuits for low-voltage flash memories”, IEEE JSSC, Vol. 34, No. 8, Aug. 1999, pages 1091-1098. Therein are described the advantages of using the charge pump for generating the high voltage, since the circuit region and the operational currents of the charge pump are low compared to other periphery circuit components.
Meanwhile, a row decoder adapted in a NOR type flash memory device must be able to supply different levels of voltages from a negative high-voltage to a positive high-voltage due. This is because of the flash memory as described above. In general, a high voltage refers to a voltage having a potential higher than the potential of the voltage of the power supply. That is, in the case of a 3/3V power supply voltage, about 4.5V can be applied to the selected word line on a read-out operation, about 9V can be applied to the selected word line on the programming operation, and about 9V and −9V can be applied to the word line and the bulk region, respectively, on the erasure operation. One circuit supplying such voltages, as well as the row decoder and its associated circuits in conventional device are illustrated in FIG.
1
.
In
FIG. 1
, memory cell sectors
13
and
14
correspond to, for example, i
th
and j
th
sectors, respectively, with the total memory cell array divided into a plurality of sectors, each sector comprising 1024 word lines and 512 bit lines having 64(K) (k=1024) byte memory capacity (64(k) (b)ytes=1024*512bits). In a read-out operation or a programmable operation, selection of a word line requires 10 address signals corresponding to 1024 word lines. One of 128 global word lines is selected by a global row decoder
10
and one of eight local word lines allocated to one global word line (128*8=1024) is selected by a local row decoder
15
or
16
. The word line driver WD allocated to each word line, drives its associated word line in response to a global word line selection signal GWL supplied from the global row decoder
10
, a local word line selection signal PWL supplied from the local row decoder
15
or
16
, and a block selection signal BLS supplied from the block decoder
17
or
18
. To supply a high voltage (a positive high voltage or a negative high voltage) to a word line in a read-out operation, a program operation or an erase operation, the global row decoder
10
and the local row decoder
15
or
16
are arranged with a level shifter LS for switching the high voltages.
FIG. 2
illustrates the connective relationship between the word line drivers WD
0
~WD
7
and the LS
0
that is one of 128 level shifters embedded in the global row decoder
10
.
FIG. 3
illustrates the structure of LS
0
i
that is one of eight level shifters embedded in the local decoder
15
. In
FIG. 2
, the voltage terminal VPP represents a positive high voltage for a program operation and VEX represents a negative high voltage for an erase operation. As shown in FIG.
2
and
FIG. 3
, the high-voltage type PMOS transistors PH
1
~PH
11
and the high-voltage type NMOS transistors NH
1
~NH
11
are used to switch the high voltages.
The high-voltage type transistors are the transistors designed to perform the switching function without a physical burden such as a breakdown of an insulating film. Such transistors reinforce the enhancement characteristic of the MOS transistor even if a voltage higher than a voltage of the power supply may be applied to the drain or the source. In a read-out operation or a program operation, the positive high voltage VPP is switched to the corresponding word line, for example WL
0
i
through the high-voltage type PMOS transistors PH
1
, PH
11
, and PH
3
. In an erase operation, the negative high-voltage VEX is switched to the corresponding word line through the high voltage type NMOS transistors NH
2
and NH
4
. The voltages applied according to the respective operation mode is listed in table 1 below:
TABLE 1
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