Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-02
2003-05-06
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S355000
Reexamination Certificate
active
06559503
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a transistor which is protected against electrostatic discharges. The device has a substrate, doped source and drain diffusion regions formed in the substrate, a channel region which lies between the source and drain diffusion regions and extends in a direction along these regions, and a plurality of insulating, strip-type zones provided in the source and/or drain diffusion region in order to increase the electrical sheet resistance thereof.
Chips require protection against electrostatic discharges (ESD). Therefore, a multiplicity of ESD protection elements are situated in all chips. Furthermore, the active elements of the chips, in particular the driver transistors, have to be protected against ESD.
An essential measure for protecting transistors consists in positioning series resistors upstream of the drain and/or source electrodes of the transistors. The series resistors lead to a more homogeneous current flow during an ESD event and reduce the risk of failures as a result of current focusing. The resistors must neither be too small (this brings about an inhomogeneous current flow, which results in inadequate ESD strength) nor too large (this brings about an excessively high voltage drop in the event of large currents and hence no longer a protective effect).
A customary measure for implementing such series resistors consists in providing a sufficiently long diffusion region between the corresponding contact holes (drain contact hole and source contact hole, respectively) and the gate electrode of the MOS transistor. The diffusion region length which is necessary for the series resistor required results from the sheet resistance of the diffusion region and the desired value for the series resistor. What is disadvantageous about this procedure is that—also on account of the siliciding of the connection structures which is carried out as standard in semiconductor technology—comparatively long diffusion regions are required, resulting in a high area occupancy.
An alternative procedure for increasing the series resistance of the source and/or drain electrodes consists in the siliciding of the connection structures which is provided as standard being prevented, at least in regions, in the region of the diffusion region by means of a masking step (so-called “silicide blocking mask”). That technique is described in U.S. Pat. No. 6,046,087. The omission—in regions—of the silicide layer having a high electrical conductivity above the diffusion region makes it possible to reduce the length of the diffusion region without impairing the ESD strength of the component.
U.S. Pat. No. 5,721,439, which represents the closest prior art of which we are aware, describes a MOS transistor (MOS: Metal Oxide Semiconductor) wherein strip-type islands of reduced electrical sheet resistance are produced in the silicided drain and source diffusion regions. The islands bring about an increase in the diffusion resistances in the regions of the current feeders for the drain and source electrodes. The individual islands are oriented perpendicularly to the direction of current flow (i.e. parallel to the gate) and are arranged offset with respect to one another. They form current barriers by means of which the current is distributed over the entire available area of the diffusion regions. What is disadvantageous, however, is that, on account of the winding current path, current constrictions or inhomogeneities can occur which adversely affect the ESD strength.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a transistor with ESD protection, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for a transistor that exhibits a high ESD strength in conjunction with short diffusion distances. It is a particular object of the invention that the driver capability of the transistor should not be impaired by the ESD protection measures.
With the foregoing and other objects in view there is provided, in accordance with the invention, a transistor, comprising:
a substrate;
doped source and drain diffusion regions formed in the substrate;
a channel region disposed between the source and drain diffusion regions and extending in a first direction along the source and drain diffusion regions;
a plurality of strip-shaped insulating zones in at least one of the source and drain diffusion regions for increasing an electrical sheet resistance thereof;
the strip-shaped insulating zones extending along a second direction oriented substantially perpendicular to the first direction of the channel region; and
the strip-shaped insulating zones having ends facing the channel region and spaced apart from the channel region.
In other words, the basic concept of the invention consists in strip-type, insulating zones being oriented essentially perpendicularly to the profile of the channel region of the transistor. The result of this is that the direction of current flow corresponds to the longitudinal direction of the insulating zones. As a result, an essentially homogeneous current transport is maintained over the entire diffusion region. This increases the ESD protective effect since current constrictions or focusing are avoided in the region of the diffusion region. At the same time, the desired effect of increasing the diffusion resistance is achieved through the reduction of the effective area available for current conduction.
The term “insulating zones” as used herein also encompasses zones of reduced electrical conductivity. A complete and absolute insulation effect is not necessary.
The spacing left between the channel region and those ends of the insulating zones which face the channel region has the effect that the current passed between the insulation ribs can be distributed again directly upstream of the channel region (or upstream of the gate electrode in the case of a MOS transistor). The advantage of this measure is that the driver capability of the transistor is not impaired by the insulating zones, since the entire width of the channel region remains usable.
In accordance with a preferred embodiment of the invention, the transistor is a MOS transistor having a gate electrode assigned to the channel region or a lateral bipolar transistor.
An advantageous embodiment of the transistor according to the invention is wherein the distances between those ends of the insulating zones which face the channel region and the channel region are between 0.02 and 1.0 &mgr;m. With such dimensioning, the two aspects of a high driver capability and a good ESD protection effect are taken equally into account.
For reasons of obtaining a high current homogeneity, the strip-type, insulating zones are preferably arranged essentially parallel and at approximately the same transverse distance with respect to one another. That is, in accordance with an added feature of the invention, the strip-shaped insulating zones are arranged substantially parallel to and substantially equidistant from one another along the first direction.
Since the strip-type, insulating zones are oriented in the direction parallel to the direction of current flow, the zones can readily have a continuous profile, i.e. perforations in the zones are not necessary.
Preferably, a sheet resistance of the drain and/or source diffusion region which lies between 50 and 300 &OHgr;/□, in particular 80 and 150 &OHgr;/□, is set by means of a suitable dimensioning of the insulating, strip-type zones. A sheet resistance of this magnitude is optimal for enabling short diffusion distances in conjunction with good ESD protection.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a transistor with ESD protection, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without
Guggenmos Xaver
Stadler Wolfgang
Wendel Martin
Fahmy Wael
Farahani Dana
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
LandOfFree
Transistor with ESD protection does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor with ESD protection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor with ESD protection will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3003225