Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-30
2003-03-04
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S627000, C438S637000, C438S644000, C438S687000
Reexamination Certificate
active
06528412
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of interconnect, such as copper interconnect for example, within an integrated circuit, and more particularly, to depositing an adhesion skin layer and a thin conformal seed layer for filling an interconnect opening to minimize electromigration and void formation within the interconnect.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to
FIG. 1
, a cross sectional view is shown of a copper interconnect
102
within a trench
104
formed in an insulating layer
106
. The copper interconnect
102
within the insulating layer
106
is formed on a semiconductor wafer
108
such as a silicon substrate as part of an integrated circuit. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect
102
is typically formed by etching the trench
104
as an opening within the insulating layer
106
, and the trench
104
is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to
FIG. 1
, the insulating layer
106
may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO
2
) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer
106
, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material
110
is deposited to surround the copper interconnect
102
within the insulating layer
106
on the sidewalls and the bottom wall of the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material
110
is disposed between the copper interconnect
102
and the insulating layer
106
for preventing diffusion of copper from the copper interconnect
102
to the insulating layer
106
to preserve the integrity of the insulating layer
106
.
Further referring to
FIG. 1
, an encapsulating layer
112
is deposited as a passivation layer to encapsulate the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer
112
is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect
102
does not easily diffuse into such a dielectric of the encapsulating layer
112
.
Referring to
FIG. 2
, typically for filling the trench
104
with copper, a diffusion barrier material
121
is deposited on the sidewalls and the bottom wall of the trench
104
. The diffusion barrier material
121
is similar to the diffusion barrier material
110
of
FIG. 1. A
seed layer
122
of copper is deposited on the diffusion barrier material
121
at the sidewalls and the bottom wall of the trench
104
, and then copper is electroplated from the seed layer
122
to fill the trench
104
in an ECD (electrochemical deposition) process, as known to one of ordinary skill in the art of integrated circuit fabrication. The seed layer
122
of copper is typically deposited by a PVD (plasma-vapor-deposition) process as known to one of ordinary skill in the art of integrated circuit fabrication. With such a deposition process, referring to
FIG. 2
, when the aspect ratio (defined as the depth to the width) of the trench
104
to be filled with copper is relatively large (i.e., greater than 5:1), the seed layer
122
that is deposited on the sidewalls and the bottom wall of the opening
104
may have a significant overhang
124
at the top corners of the interconnect opening
104
.
Referring to
FIGS. 2 and 3
, when copper fill
126
is plated from the seed layer
122
, the copper that is plated from the overhang
124
may close off the top of the interconnect opening
104
before a center portion of the interconnect opening
104
is filled with copper to result in formation of a void
128
within the copper fill
126
toward the center of the interconnect opening
104
. Such a void
128
disadvantageously increases the resistance of the interconnect and may even contribute to electromigration failure of the interconnect.
Referring to
FIG. 4
, to minimize the overhang
124
at the top corners of the interconnect opening
104
, the seed layer of copper
122
is deposited to be thinner. However, the deposition of the seed layer
122
is not perfectly conformal when the seed layer
122
is too thin (having a thickness of less than about 100 angstroms) when the conventional PVD (plasma-vapor-deposition) process for depositing the seed layer
122
is used. The seed layer
122
may be discontinuous and may not form at the sidewalls and the bottom corners of the interconnect opening
104
. However, it is desired for the copper fill to be plated from substantially all surfaces of the interconnect opening
104
including substantially the whole surface of the sidewalls and the bottom corners of the interconnect opening
104
to prevent void formation. Nevertheless, a thinner seed layer
122
is also desired to avoid formation of the overhang
124
for the interconnect opening
104
having high aspect ratio.
Referring to
FIG. 5
, because the seed layer
122
is discontinuous when the seed layer
122
is too thin, a seed enhancement layer
130
is formed on the seed layer
122
. The seed enhancement layer
130
is a thinner layer of copper (having a thickness of about 50 angstroms to about 500 angstroms). The seed enhancement layer
130
is formed by an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process instead of the conventional PVD (physical-vapor-deposition) process (for forming the seed layer
122
) such that the seed enhancement layer
130
is conformal to continuously cover substantially all exposed surfaces within the interconnect opening
104
. A copper fill
132
is then plated from the seed enhancement layer
130
and the seed layer
122
.
However, because the seed enhancement layer
130
is formed by an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process instead of the conventional PVD (physical-vapor-deposition) process for forming the seed layer
122
, the seed enha
Lopatin Sergey
Wang Pin-Chin C.
Choi Monica H.
Guerrero Maria
Zarabian Amir
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