Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-10-10
2003-09-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S300000, C438S976000
Reexamination Certificate
active
06627527
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process sequence for forming metal silicide layers with reduced porosity and voids.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, has allowed device performance to be increased while the processing costs for these same devices have been reduced. The use of sub-micron features have allowed performance degrading junction capacitances to be reduced, while the number of smaller semiconductor chips realized from a specific size semiconductor wafer have allowed the processing costs for a specific semiconductor chip to be reduced. However specific aspects of micro-miniaturization can present fabrication situations which have to be addressed. For example the narrower channel regions now available with micro-miniaturization result in word line widths of 0.20 um or less. To adequately reduce word line resistance for narrow word lines optimum self-aligned metal silicide (salicide), layers are needed, formed overlying conductive gate structures. However voids in the metal silicide layer, or agglomerated metal silicide regions, can adversely influence the resistance of the narrow word lines to a greater degree than similar voids or for agglomeration metal silicide regions overlying wider gate structures.
One aspect of the salicide process which can result in voids or agglomeration adversely influencing salicide resistance, is the process used to selectively remove unreacted metal from regions in which the metal layer overlaid non-silicon regions. This process step is performed after a first anneal procedure is used to form a first phase metal silicide layer on conductive areas of a metal oxide semiconductor field effect transistor (MOSFET), device, areas such as source/drain regions and conductive gate structures. The selective removal of unreacted metal is performed in wet solutions containing components that can be incorporated into the first phase metal silicide layer. A subsequent second anneal procedure used to convert the first phase metal silicide layer to a lower resistance, second phase metal silicide layer, can not remove the incorporated components of the previously performed selective wet removal procedure, thus allowing the incorporated components of the selective wet removal procedure to remain in the final, or second phase metal silicide layer, during this anneal procedure resulting in unwanted voids and agglomerated metal silicide regions.
The present invention will teach a process for removing the components incorporated into a first phase metal silicide layer during the wet etch procedure used to selectively remove unreacted metal, prior to initiation of a final anneal procedure used to form the low resistance, second phase metal silicide layer, thus reducing metal silicide voids and agglomerated regions. Prior art, such as Han, in U.S. Pat. No. 6,207,562 B1, Adetut et al, in U.S. Pat. No. 6,136,678, Subrahmanyan et al, in U.S. Pat. No. 6,107,192, and Sumi et al, in U.S. Pat. No. 5,194,405, describe methods of forming metal silicide layers on regions of a semiconductor device. However none of the above prior art describe the novel process sequence employed in the present invention in which a critical process step is performed after selective removal of unreacted metal, and before a final anneal procedure used to convert a high resistance metal silicide phase to a lower resistance metal silicide phase. The critical process step removes components incorporated into the high resistance metal silicide phase, components that were incorporated into the metal silicide layer during the procedure used to remove unreacted metal. The removal of these incorporated species reduce the risk of voids or agglomeration in the lower resistance, final metal silicide phase.
SUMMARY OF THE INVENTION
It is an object of this invention to form a low resistance metal silicide layer on a word line structure of a MOSFET device.
It is another object of this invention to perform a procedure to remove components incorporated into a high resistance first metal silicide layer during the selective removal of unreacted metal, with the procedure performed at a stage of the salicide process sequence prior to employment of a final anneal procedure which is used to convert the high resistance first metal silicide layer to a lower resistance second metal silicide layer.
It is still another object of this invention to remove the components incorporated into the high resistance first metal silicide layer during removal of unreacted metal, via a medium temperature, high vacuum procedure.
In accordance with the present invention a method of forming metal silicide on a word line structure featuring a medium temperature, high vacuum anneal procedure, used to remove components incorporated into a metal silicide layer during a procedure used to selectively remove unreacted metal, is described. After definition of a conductive gate structure, and formation of insulator spacers on the sides of the conductor gate structure, a metal layer is deposited. A first anneal procedure is employed to form a high resistance metal silicide phase on the top surface of the conductive gate structure, while areas in which the metal layer overlaid insulator remain unreacted. Removal of unreacted metal is accomplished via selective wet etch procedures, with components of the wet etch solution incorporated into the high resistance metal silicide phase. A high vacuum, medium temperature anneal procedure is used to remove the incorporated components of the selective wet etch procedure from the high resistance metal silicide layer. A second anneal is next performed to convert the high resistance metal silicide layer, now free of incorporated components of the selective wet etch procedure, to a low resistance metal silicide layer, resulting in a word line structure comprised of the low resistance metal silicide layer on the underlying conductive gate structure.
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Chang Chi-Wei
Shue Winston
Wang Maureen
Ackerman Stephen B.
Lindsay Jr. Walter L.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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