Nonvolatile semiconductor memory capable of random programming

Details Nonvolatile semiconductor memory capable of random programming Nonvolatile semiconductor memory capable of random programming

2002-02-21

2003-01-07

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185290, C365S185180, C257S316000

Reexamination Certificate

active

06504763

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a NAND type nonvolatile semiconductor memory capable of random programming.
2. Description of the Prior Art
Recently, flash electrically erasable programmable read-only memories (EEPROMs) have gained substantial interest as the best solution for electrically rewritable high-density nonvolatile data storage. These semiconductor memories combine the high integration density and the high programming speed of EPROMs with the higher functionality of EEPROMs by offering electrical in-circuit erasability. Typically, flash memory includes both NOR cell and NAND cell types.
At first, the flash memory was introduced to replace program code EPROMs and battery-backed Random Access Memories (RAMs) in measuring equipment for calibration and data storage, and in microcomputers for micro-code updates.
Nowadays, new applications have arisen such as solid-state disks for small computers and Personal Digital Assistants (PDAs), program storage for portable equipment, and smart cards. The NAND cell type flash memory is especially widely utilized in various fields. Furthermore, the operational mechanism of many commercially available flash EEPROM devices can be divided into several classes. One class of flash EEPROMs uses a bi-directional Fowler-Nordheim (FN) tunneling mechanism to function.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional view illustrating a conventional NAND type EEPROM
10
. As shown in
FIG. 1
, the NAND type EEPROM
10
comprises a semiconductor substrate
12
having a memory region, a semiconductor well
14
located in the semiconductor substrate
12
within the memory region, a plurality of NAND cell blocks B located on the semiconductor substrate
12
within the semiconductor well
14
, and a bit line BL
1
located over the semiconductor substrate
12
.
Furthermore, the NAND cell block B comprises a plurality of rewritable memory cell transistors M connected in series along a direction of the bit line BL
1
. Meanwhile, adjacent memory cell transistors M underneath the same bit line BL
1
share diffusion regions in the semiconductor well
14
as their sources and drains so as to constitute a NAND cell. For example, a memory cell transistor M
114
utilizes a diffusion region
16
as its source and a diffusion region
18
as its drain. Simultaneously, the diffusion region
18
is the source of a memory cell transistor M
115
as well.
Additionally, the memory cell transistor M has a stacked gate structure. For instance, the memory cell transistor M
114
has a floating gate
22
for storing charge, an insulator film
24
, and a control gate
20
which are stacked up on the semiconductor well
14
. Moreover, a selecting transistor ST is located at one end of the series array of rewritable memory cell transistors M and is electrically connected to a source line SL. In addition, a plug
26
is located at the other end of the series array of rewritable memory cell transistors M and is electrically connected to the bit line BL
1
. At the same time, the control gate
20
of the memory cell transistor M is electrically connected to a word line perpendicular to the bit line BL
1
. Thus, the series array of memory cell transistors M driven by the same word line defines one NAND cell block B.
For the prior art NAND type EEPROM
10
, a programming operation is carried out by applying a high voltage such as 20V to a selected word line. Meanwhile, a rather high voltage such as 12V is applied to unselected word lines to conduct a channel. Consequently, the prior art NAND type EEPROM
10
has very high power consumption. In addition, since each of the word lines are required to have high voltages applied to them, the programming speed is decelerated and corresponding reliability problems such as junction breakdown will occur.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a NAND type nonvolatile semiconductor memory capable of random programming to solve the above-mentioned problems.
According to the claimed invention, a nonvolatile semiconductor memory capable of random programming comprises a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of the first conductivity type isolated by an STI layer within the deep ion well, at least one NAND cell block located on the semiconductor substrate within the shallow ion well, and a bit line located over the semiconductor substrate used to provide a first predetermined voltage for the shallow ion well during a data program mode and provide a second predetermined voltage for the shallow ion well during a data erase mode via a conductive plug which electrically connects to the bit line and extends downward to the shallow ion well.
It is an advantage of the claimed invention that a nonvolatile semiconductor memory comprises a shallow ion well within a deep ion well, and a conductive plug which extends downward to the shallow ion well to be a common electrode, so that requirement of applying high voltages to each word line is unnecessary during a programming operation. That is, according to the claimed invention nonvolatile semiconductor memory, during a programming operation, only a selected word line is required to have an appropriate voltage applied to it. Thus, the power needed is substantially reduced and the access time is shortened. Consequently, the performance of the nonvolatile semiconductor memory is significantly improved.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 6295227 (2001-09-01), Sakui et al.
patent: 6400604 (2002-06-01), Noda

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