Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2001-03-21
2002-10-29
Oda, Christine K. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S601000
Reexamination Certificate
active
06472886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit (IC), and more particularly to a method of calculating parasitic capacitances and their effects on floating conductive patterns used in ICs.
2. Description of the Related Art
Many insulating layers and conductive patterns are stacked on a substrate, realizing an integrated circuit (IC). However, as the IC becomes more highly-integrated, vertical and horizontal intervals between interconnections (electrodes) become narrower. The effects of parasitic capacitances between the narrower interconnections become more pronounced. Parasitic capacitances can cause is undesirable effects such as signal delay and crosstalk. Therefore, the existence of parasitic capacitances must be anticipated and it is common practice to calculate the parasitic capacitance when designing ICs.
Poisson's equation, expressed as in Equation 1, is commonly used in the calculation of parasitic capacitance:
G
2
&phgr;=P
where &phgr; is the potential function at a predetermined position, and p is a function or constant that is pre-assigned according to the problem to be solved. The potential &phgr;, is obtained by solving Poisson's equation in Equation 1 and the capacitance C is obtained by Equation 2a and 2b.
C
=
Q
V
(2a)
Q=∫{right arrow over (E)}·dS=∫∇
&phgr;
·dS
(2b)
where Q is charge, V is voltage, {right arrow over (E)} is the electric field, [and S is distance?].
Here, boundary conditions are usually required to solve Poisson's equation. In IC manufacture, boundary conditions are usually set with the Dirichlet condition for designating a potential value at a predetermined node and the Neumann condition for designating a gradient value of the potential at a predetermined node.
Another factor to consider is that dummy conductive pattern, having no electrical role, are often added to ICs for any number of reasons. For example, in the process of fabricating an IC there may be a dummy pattern for compensating for a step difference formed on a portion of an IC chip, or for preventing a dishing phenomenon in which the insulating layer becomes dented where the patterns are sparse, such as during the planarizing of an insulating layer in a chemical mechanical polishing (CMP) process. In general, a voltage is not applied to these dummy conductive patterns, and they remain in an electrically isolated state, that is, in a floating state. Often, separate interconnections are provided to apply a voltage to the dummy conductive patterns or to ground them, thereby contributing further to the overall parasitic capacitance. Similarity, a floating gate of a non-volatile memory device is another example of a floating conductive pattern, even if the floating gate is not a dummy gate.
Because floating conductive patterns contribute to parasitic capacitance between interconnections, they are commonly included in calculations of parasitic capacitance. However, for the floating conductive patterns, it is not possible to set up the Dirichlet condition or Neumann condition as the boundary conditions for solving Poisson's equation, unless interconnections are provided to ground or apply voltage to them. In such cases, it is common to use either an “equivalent circuit” method or a “charge boundary” method. An equivalent circuit method obtains the capacitance by assuming the floating conductive patterns as the electrically connected interconnections, in which the Dirichlet conditions can be set up. A charge boundary method obtains the potential by non-linear iteration by setting-up an arbitrary charge condition on the floating conductive patterns.
However, the calculation of capacitance by the equivalent circuit and charge boundary methods as applied to floating conductive patters is more complicated and requires more time than the calculation of the capacitance between actual interconnections (electrodes).
It would therefore be desirable to provide a method of calculating parasitic capacitance that requires less computing time than the traditional equivalent circuit and charge boundary methods, particularly in situations where floating conductive patterns are present.
SUMMARY OF THE INVENTION
Disclosed herein is a method of calculating capacitance between conductive patterns of an integrated circuit (IC) comprising defining a mesh of nodes in a space between at least two electrodes, calculating the electric potential at each said node, and calculating the parasitic capacitance between said electrodes.
The method preferably further comprising one or more floating conductive patterns between said electrodes and wherein a set of surface nodes is defined upon the outer surface of each said floating conductive pattern. The surface nodes are mathematically treated as a single merged node for each said floating conductive pattern, wherein said electric potentials are calculated by a linear equation of the form:
{overscore (A)}{right arrow over (&phgr;)}={right arrow over (b)}
where {right arrow over (&phgr;)} is a potential vector of N potentials corresponding to each of N said nodes in said mesh; {overscore (A)} is the matrix of coupling coefficients between said nodes, and {right arrow over (b)} is a vector of known constant or function.
According to an of the present invention, a recording medium, is provided for storing a program executable by computer for calculating parasitic capacitance between conductive patterns of an integrated circuit (IC) having two electrodes, the program comprising: a module for defining a mesh of nodes in a space between said electrodes; a module for calculating the electric potential at each said node; and a module for calculating the parasitic capacitance between said electrodes from said electric potential.
Preferably, the recording medium further includes a module for merging surface nodes of floating conductive patters into a single merged node for each said floating conductive pattern by using an equivalent potential condition at the surfaces of the floating conductive patters, wherein said module for calculating electric potential utilizes a linear matrix equation of the form:
{overscore (A)}{overscore (&phgr;)}={right arrow over (b)}
where {overscore (&phgr;)} is a potential vector of N potentials corresponding to each of N said nodes in said mesh; {overscore (A)} is the matrix of coupling coefficients between said nodes, and {right arrow over (b)} is a vector of known constant or function.
REFERENCES:
patent: 6327545 (2001-12-01), Browen
patent: 2002/0036508 (2002-03-01), Komoda
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