Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-19
2002-12-10
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S638000, C438S643000, C438S678000, C438S692000
Reexamination Certificate
active
06492270
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of forming a copper damascene interconnect with an integrated process using a copper via plug.
(2) Description of the Related Art
Conventional techniques of fabricating a dual damascene structure usually starts with the forming of an intermetal dielectric (IMD) layer over a semiconductor substrate, followed by the etching of the IMD to define the via and trench openings that will hold the metal wiring. The vertically connected via/trench openings together form the dual damascene structure, as it will be described more in detail later. Prior to filling with copper as the filler metal, the via and trench openings are first lined with a barrier material in order to prevent copper diffusion into the surrounding IMD layer. The barrier material is further lined with a copper seed layer in order to improve the adhesion of the yet-to-be deposited bulk copper to the barrier material. Finally, the via/trench dual damascene structure is filled with copper by using electroplating techniques. Any excess copper metal over and above the surface of the dual damascene structure is removed by chemical mechanical polishing (CMP), as is well known in the art. However, what is being realized more and more in the semiconductor art is that the conventional methods of forming dual damascene structures such as briefly described above are becoming inadequate to satisfy the stringent topology requirements of the continuously shrinking feature sizes—in some cases as low as 0.10 micrometers (&mgr;m)—of the deep-submicron technologies of to-day. A case in point is the non-uniformity of a copper seed layer over a barrier layer in high aspect ratio openings, as it will be appreciated by those skilled in the art. It is disclosed later in the embodiments of the present invention a method of avoiding such non-uniform topologies in the forming of copper dual damascene structures.
Copper is a preferred metal for use as an interconnect in semiconductor devices. This is because, as is well known in the art, copper has lower resistivity than the commonly used aluminum and has better electromigration properties. At the same time, the advent of copper interconnects has motivated the use of insulating materials with low dielectric constant (k) in order to further improve the over-all device performance. Some of the low-k candidates are fluorinated materials, such as amorphous fluorinated carbon (&agr;-C:F), PTFE, fluorinated SiO
2
and fluorinated polyimide. However, defluoriniation occurs with these materials, which then reacts with barrier materials and causes delamination. Barrier materials are used because, copper unfortunately suffers from high diffusivity in these insulating materials. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
Copper dual damascene process is a well-known technique for forming interconnections in semiconductor devices. It is especially well suited for Ultra Large Scale Integrated (ULSI) circuit technology where more and more devices are being packed into the same or smaller areas in a semiconductor substrate. As the feature sizes get smaller, the smaller geometries result in higher electrical resistances, which in turn degrade circuit performance. As will be described more fully later, damascene process provides a more exact dimensional control over small geometries, while copper, as the metallization material, provides better electrical characteristics.
The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, grooves and holes in appropriate locations in the grooves are formed in an insulating material by etching, which are then filled with metal. Metal in grooves form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, hole openings are also formed at appropriate places in the groove further into the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process shown in
FIG. 1
a,
two insulating layers (
120
) and (
130
) are formed on a substrate (
100
) with an intervening etch-stop layer (
125
). Substrate (
100
) is provided with metal layer (
110
) and a barrier layer or passivation layer (
115
). Metal layer can be the commonly used aluminum or copper, while the barrier layer can be an oxide layer or nitride layer. A desired trench or groove pattern (
150
) is first etched into the upper insulating material (
130
) using conventional photolithographic methods and photoresist (
140
). The etching stops on etch-stop layer (
125
). Next, a second photoresist layer (
160
) is formed over the substrate, thus filling partially the groove opening (
150
), and patterned with hole opening (
170
), as shown in
FIG. 1
b.
The hole pattern is then etched into the lower insulating layer (
120
) as shown in
FIG. 1
c
and photoresist removed, thus forming the dual damascene structure shown in
FIG. 1
f.
Or, the order in which the groove and the hole are formed can be reversed. Thus, the upper insulating layer (
130
) is first etched, or patterned, with hole (
170
), as shown in
FIG. 1
d.
The hole pattern is also formed into etch-stop layer (
125
). Then, the upper layer is etched to form groove (
150
) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (
120
), as shown in
FIG. 1
e.
It will be noted that the etch-stop layer stops the etching of the groove into the lower insulation layer.
After the completion of the thusly formed dual damascene structure, both the hole opening and groove opening are usually filled with metal (
180
), and any excess material on the surface of the substrate is removed by chemical mechanical polishing (CMP), as shown in
FIG. 1
f.
In prior art, both electroless and electroplating techniques have been used in forming interconnects on a semiconductor substrate. Thus, in U.S. Pat. No. 5,891,513, Dubin, et al., disclose a method where once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and harrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric harrier layer. The copper interconnect is fully encapsulated from the adjacent material
Ackerman Stephen B.
Nguyen Ha Tran
Saile George O.
Taiwan Semiconductor Manufacturing Company
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