Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-10-12
2002-10-08
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06462995
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having built-in self-test function in which a test function is incorporated in a chip so as to reduce overhead of its chip area and simplify processing steps.
2. Description of the Background Art
With recently increased scale of LSI, system LSI containing a large capacity memory such as SRAM, DRAM and flash memory has appeared. Generally, these memory cells use stricter processing rules than other logic area for high integration and their critical area (area designed based on minimum processing rule) is enlarged. Therefore, a yield rate of the memory cell is lower than other logic portions.
To solve this problem, the memory that is incorporated in system as well as general purpose memory is provided with a defective memory recovery means such as a redundancy circuit and employs a method for increasing the yield rate of the system LSI.
FIG. 1
shows an example of configuration of memory redundancy circuit. Referring to
FIG. 1
, a proper memory array
100
is composed of m rows x n columns and a row decoder
101
selects a desired row (i-th row). As a result, all memory cells connected to the i-th row are activated. Each column is connected to n-bit bus line through a reading circuit
102
and a writing circuit
103
. A content of the memory cell is accessed by the reading circuit
102
and writing circuit
103
of the memory cell connected to the selected i-th column.
In such a configuration, to enable recovery of the defective bit of, for example, 1 bit, a redundant bit column
104
is disposed in the vicinity of the proper memory array
100
.
Usually, a reading circuit
102
and writing circuit
103
equivalent to the reading circuit and writing circuit of the proper memory array
100
are connected to this redundancy bit column
104
in redundant condition.
If there is a defective bit in the j-th row and k-th column, all memory cells of the k-th column in both the reading circuit and writing circuit are inhibited to use. Then, the memory cell column of the (k+1)-th column, reading circuit
102
and writing circuit
103
are connected to the k-th bit bus line. Next, a memory cell column of the (k+2)-th column, reading circuit and writing circuit are connected to the bus line of the (k+1)-th bit. That is, the connection to the bus line is shifted by
1
bit. A memory cell column of a redundant bit column
104
, reading circuit and writing circuit are connected to the bus line of the n-th bit. This recovery method for redundancy is called shift redundancy. This shift redundancy is a very effective method for a memory having a large bus width like a memory incorporated in system LSI. As a result, a proper function of the memory is never lost even if a defective bit of 1 bit exists.
Therefore, even if there is found a defective bit, it can be recovered so that the yield rate is improved remarkably.
FIG. 2
shows a structure of a program circuit
105
(shown in
FIG. 1
) for achieving the aforementioned bit shift. In
FIG. 2
, this program circuit
105
is disposed at each bit column.
Usually, both inputs of logical product (AND) gate
106
are of high level, and the bit column and bus line of the proper memory array
100
are connected to each other corresponding to the same bit column by a multiplexer (MUX)
107
.
If the redundancy of a memory cell of the k-th column is achieved, the fuse
108
composed of metallic wiring layer or polysilicon wiring layer corresponding to the k-th column is melted down with the use of laser beam or the like, so that one input of the AND gate
106
becomes low level. Then, the MUX
107
connects the (k+1)-th column of the proper memory array to the bus line of the k-th bit and the output of the AND gate of the k-th column is transmitted to all the AND gates
106
of the upper side. Then, the upper bit MUX after the k-th bit selects the upper bit column and connection is shifted from the k-th column including the defective bit to adjoining (k+1)-th column. Because this shift information is propagated to the program circuits
105
from the k-th bit to the n-th bit through the AND gate
106
. Therefore, single defective bit can be repaired by melting of single fuse
108
.
However, because the aforementioned redundancy recovery method using the fuse facilitates melting down of the fuse, first, additional processing step such as thinning of the protective film on the fuse is necessary for easy melt down. Second, because the fuse is melted down by laser beam, the fuse layout pattern cannot be decreased in size and further, any active element or wiring layer cannot be disposed in the fuse region. Thus, there is a problem that the overhead of area is increased.
FIG. 3
shows a flowchart of a test process for system LSI including a redundant circuit by BIST (built-inself-test). In this BIST, first, memory test is carried out on the wafer (step S
10
) and the fuse
108
of a column including the defective bit is melted down (step S
11
). The memory test is carried out again on the wafer in which connection is shifted (step S
12
) and die sort by function test is carried out (step S
14
). Memory test (step S
15
) in package and final test (step S
16
) are carried out.
As shown in
FIG. 3
, the redundancy recovery method using the fuse has such a problem that a post process for melting of the fuse and an additional memory test after the melting of the fuse are necessary. Further, if any defective bit is contained in the memory cell from the beginning, the logical circuit having no redundancy means cannot be tested sufficiently in the first memory test and therefore, additional test must be carried out after the redundancy processing. Therefore, there is another problem that the test cost is increased.
To solve such a problem, the BISR (built-in self-repair) method has been proposed, in which the defective bit is extracted using the aforementioned BIST method and then this defective bit information is memorized in a register so as to realize the melting of the fuse.
FIG. 4
shows an example of a structure of the self-test circuit of the memory using the BIST. Referring to
FIG. 4
, the BIST comprises an address pattern generator
111
for a test target memory
110
, a data pattern generator
112
, an expected value generator
113
b
and a comparator
113
for comparing an expected value attached to the bus of each bit with read out data. Then, the BIST realizes a function of memory tester in a LSI chip so as to determine whether the memory array is acceptable. In the aforementioned, the register is connected to an output of this comparator
113
and a result of determining whether or not the bit is acceptable is stored in this register. This register plays the same role as the aforementioned fuse, so that connection is shifted to adjoining memory cell column without using a memory cell column in which the defective cell exists.
FIG. 5
shows an example of the structure of the BISR. In this BISR circuit, data read out from the memory cell is compared with an expected value and a result of the comparison is stored in the register and bit shift is realized for recovery of the defective bit depending on the storage content. In
FIG. 5
, the readout data amplified by a sense amplifier (S/A)
114
is compared with the expected value in an exclusive NOR (EX-NOR) gate
115
and this comparison result is held by the register
116
. If the comparison result does not coincide, “0” is held by the register
116
and this information is propagated to the upper bit side through the AND gates
117
,
118
. As a result, the shift to the upper bit is carried out by the MUX
119
as described above, so that the defective bit column is replaced with the redundant bit column.
However, this BISR method of holding information of the defective cell in the register
116
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Phan Trong
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