Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-06-30
2002-12-17
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C327S142000
Reexamination Certificate
active
06496038
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to high frequency integrated circuits that include domino logic.
2. Discussion of Related Art
Advances in semiconductor manufacturing technologies have enabled circuit designers to continue to integrate more transistors on a single die. At the same time, computer architecture, and more specifically, processor architecture, continues to focus on shorter and shorter cycle times.
Domino logic is frequently used in an effort to reduce power, die area and output capacitance as compared to static full complementary metal oxide semiconductor (CMOS) logic. The reduction in parasitic capacitance provided by domino CMOS logic permits higher speed and lower power operation.
As clock speeds continue to increase (and thus, cycle times continue to decrease) and/or where certain parts of a chip operate at a much higher frequency, limitations of conventional logic circuits, including conventional domino logic circuits, may prevent such circuits from operating properly at the higher clock speeds. Further, many conventional domino logic circuits operate using a two-phase clock. For very high operating frequencies, it may not be feasible to generate and distribute a two-phase clock due to noise, clock jitter and/or other issues.
Where a pulsed clock is used instead of a conventional two-phase clock, the logic may be more susceptible to functional errors due to race conditions making such circuits more difficult for design engineers to work with.
REFERENCES:
patent: 5226011 (1993-07-01), Yanagisawa
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5467037 (1995-11-01), Kumar et al.
patent: 5491442 (1996-02-01), Mirov et al.
patent: 5517136 (1996-05-01), Harris et al.
patent: 5535343 (1996-07-01), Verseput
patent: 5708374 (1998-01-01), Durham et al.
patent: 5721875 (1998-02-01), Fletcher
patent: 5764084 (1998-06-01), Lev
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5828234 (1998-10-01), Sprague
patent: 5831932 (1998-11-01), Merritt et al.
patent: 5880608 (1999-03-01), Mehta et al.
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5942917 (1999-08-01), Chappell et al.
patent: 5952859 (1999-09-01), Kim et al.
patent: 5973514 (1999-10-01), Kuo et al.
patent: 5986475 (1999-11-01), Kim et al.
patent: 6011410 (2000-01-01), Kim et al.
patent: 6023182 (2000-02-01), Milshtein et al.
patent: 6040716 (2000-03-01), Bosshart
patent: 6094071 (2000-07-01), Ciraula et al.
patent: 6172530 (2001-01-01), Bull et al.
patent: 6201415 (2001-03-01), Manglore
patent: 6201431 (2001-03-01), Allen et al.
patent: 6204714 (2001-03-01), Milshtein et al.
patent: 6239621 (2001-05-01), Milshtein et al.
patent: 6242958 (2001-06-01), Fletcher
patent: 6275069 (2001-08-01), Chung et al.
patent: 6320441 (2001-11-01), Fletcher et al.
patent: 6331793 (2001-12-01), Fletcher et al.
patent: WO 98/29949 (1998-09-01), None
Alisa Scherer et al., An Out-of Order Three-Way Superscalar Multimedia Floating-Point Unit 1999, pp. 94-95, 449, Advanced Micro Devices, Sunnyvale, CA.
Kumar Rajesh
Murray Robert J.
Sprague Milo D.
Chang Daniel D.
Faatz Cynthia T.
Intel Corporation
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